A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.

An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

A method is provided and includes the operation below: discharging electrostatic charges from a pad to a first voltage terminal through a first active region coupled to the pad and a second active region coupled between the first active region and the first voltage terminal, in which the first active region and the second active region are the same conductivity type and have different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and discharging the electrostatic charges through an ESD primary circuit having a first terminal coupled with the first active region and a second terminal coupled with the first voltage terminal. The ESD primary circuit has a trigger voltage lower than the first breakdown voltage.

An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.

The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

A semiconductor device and a communication circuit capable of reducing the effect of a noise generated in an inductor are provided. A semiconductor device according to an embodiment includes a substrate, a first circuit disposed in a first area of the substrate, a second circuit disposed in a second area of the substrate, the second circuit being configured to operate selectively with the first circuit, a first inductor disposed in the second area and connected to the first circuit, and a second inductor disposed in the first area and connected to the second circuit.