Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A display device including a plurality of thin film transistors. One of the plurality of thin film transistors includes a gate electrode, a semiconductor layer having a region overlapping the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, a source electrode and a drain electrode in contact with a surface of the semiconductor layer opposite to the side of the gate insulating layer, and a first shield electrode arranged in a region where the source electrode and the gate electrode overlap, and a second shield electrode arranged in a region where the drain electrode and the gate electrode overlap. The first shield electrode and the second shield electrode are arranged between the gate electrode and the semiconductor layer, and are insulated from the gate electrode, the semiconductor layer, the source electrode, and the drain electrode.

Disclosed is a display device that with low power consumption. The display device includes a first thin film transistor having a polycrystalline semiconductor layer in an active area and a second thin film transistor having an oxide semiconductor layer in the active area, wherein at least one opening disposed in a bending area has the same depth as one of a plurality of contact holes disposed in the active area, whereby the opening and the contact holes are formed through the same process, and the process is therefore simplified, and wherein a high-potential supply line and a low-potential supply line are disposed so as to be spaced apart from each other in the horizontal direction, whereas a reference line and the low-potential supply line are disposed so as to overlap each other, thereby preventing signal lines from being shorted.

The present disclosure provides a wire structure for a display panel, a display panel, a display device, and a manufacturing method. The wire structure includes a first wire layer and a thermally conductive layer above the first wire layer. A thermal conductivity of the thermally conductive layer is greater than a thermal conductivity of the first wire layer.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.

The disclosure relates to the technical field of display devices and discloses a display substrate, a splicing screen and a manufacturing method thereof. The display substrate includes a flexible substrate; a plurality of signal lines located at one side of the flexible substrate; a plurality of plating electrodes located at one side of the signal lines toward the flexible substrate and electrically connected to the signal lines in one-to-one correspondence; a plurality of first through holes in one-to-one correspondence to the plating electrodes and penetrating the flexible substrate and exposing the plating electrodes, the first through roles being filled with a conductive material inside; and a plurality of binding electrodes located at one side of the flexible substrate away from the signal lines and in one-to-one correspondence to the first through holes, the binding electrodes being electrically connected to corresponding plating electrode through conductive material in corresponding first through hole.

A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.

An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

The disclosure relates to a display substrate, including: a base substrate including a display area and a peripheral area surrounding the display area; a first crack detection line located in the peripheral area and surrounding the display area; a second crack detection line located in the peripheral area and surrounding the display area; at least one first electrostatic discharge circuit located in the peripheral area, each including at least one first thin film transistor, the at least one first thin film transistor including a first gate; and at least one second electrostatic discharge circuit located in the peripheral area and electrically connected to the second crack detection line, each including at least one second thin film transistor, the at least one second thin film transistor including a second gate, wherein the second gate is electrically connected to the first gate.