To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

A method of manufacturing the display apparatus includes: attaching a removable first film to one of an upper surface and a lower surface of a substrate, adjacent to a side surface of the substrate; hydrophilic-treating a first region of the side surface of the substrate, where the side surface includes the first region and a second region; providing an organic film pattern on the first region after the hydrophilic-treating; providing a metal layer on the first region and the second region after forming the organic film pattern; and forming a connection wire by removing the organic film pattern and portions of the metal layer on the first region.

Embodiments of the present disclosure provide an array substrate comprising a base substrate, a buffer layer disposed on the base substrate, an interlayer dielectric layer disposed on the buffer layer, and a protection layer disposed on the interlayer dielectric layer, where the array substrate further comprises a plurality of first test units and a plurality of test leads. The plurality of test leads are connected to the plurality of first test units in a one-to-one correspondence, and the plurality of test leads are disposed in at least two different layers. A method for manufacturing an array substrate, a display panel, and a display device are further provided.

A liquid crystal display device includes a transistor, a pixel electrode, and a common electrode. The transistor includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a first oxide conductive layer and a second oxide conductive layer disposed between the first insulating layer and the oxide semiconductor layer and disposed with the first gate electrode and the second gate electrode sandwiched from both sides. The pixel electrode is disposed between the first and the second insulating layer; the common electrode is disposed a region overlapping with the pixel electrode and on the second insulating layer.

A display device includes a substrate, a first transistor including an oxide semiconductor layer, a first gate insulating layer, and a first gate electrode, the first transistor being provided in a display region, and a light-shielding layer provided between the substrate and the oxide semiconductor layer. The light-shielding layer includes a first light-shielding metal layer and a second light-shielding metal layer. The first light-shielding metal is provided between the substrate and the oxide semiconductor layer. The second light-shielding metal layer covers the top surface and side surface of the first light-shielding metal layer and faces the oxide semiconductor layer.

An electronic device is provided. The electronic device includes a supporting substrate, a flexible substrate disposed on the supporting substrate, a first conductive layer disposed on the flexible substrate, a second conductive layer disposed on the first conductive layer, a plurality of organic elements disposed between the first conductive layer and the second conductive layer, and an opening passing through the supporting substrate and exposing a portion of the flexible substrate. The first conductive layer alternately contacts the second conductive layer and the plurality of organic elements.

The present disclosure is related to a thin film transistor. The thin film transistor may include a gate pattern; an active layer pattern; a gate insulating layer between the gate pattern and the active layer pattern; a first conductive pattern including a first pattern part and a first connecting part ; a second conductive pattern a second pattern part and a second connecting part; and a first intermediate insulating layer between the first pattern part and the second pattern part. The first conductive pattern and the second conductive pattern may be a source pattern and a drain pattern, respectively. A first through hole may be provided on the first intermediate insulating layer. The second conductive pattern may be connected to the active layer pattern through the second connecting part in the first through hole.

A panel is provided. The display panel includes a plurality of signal lines and a plurality of transistors. The plurality of transistors are disposed in the peripheral region. Each of the plurality of transistors comprises a gate, a source and a drain. At least one of the plurality of signal lines is electrically connected to the source or the drain of one of the plurality of transistors. The at least one of the plurality of signal lines includes a turning portion. The turning portion is disposed in the peripheral region. Therefore, the panel of the disclosure can reduce the circuit placement space in the peripheral region.

Embodiments of the present disclosure provide a display panel comprising a plurality of first connecting lines and a plurality of second connecting lines which are cross-arranged, a first insulation layer, a second insulation layer defining first holes extending through the first insulation layer and the second insulation layer and second holes extending through the second insulation layer, and a plurality of third connecting lines, wherein each of the plurality of the third connecting lines is electrically connected to a corresponding one of the plurality of the first connecting lines via a corresponding one of the first hole and is electrically connected to a corresponding one of the plurality of the second connecting lines via a corresponding one of the second hole, and each of the second holes does not overlap the plurality of the first connecting lines in a top view.