H01L27/127

Thin Film Transistor Array, Fabrication Method Thereof, and Display Apparatus Comprising the Thin Film Transistor Array
20230073848 · 2023-03-09 ·

Disclosed is a thin film transistor array comprising a substrate, a first thin film transistor on the substrate, and a second thin film transistor on the substrate, wherein the first thin film transistor includes a first active layer including an oxide semiconductor on the substrate, the first active layer includes a first channel portion, a first conductor portion, and a first middle portion between the first channel portion and the first conductor portion, the second thin film transistor includes a second active layer including an oxide semiconductor on the substrate, the second active layer includes a second channel portion, a second conductor portion, and a second middle portion between the second channel portion and the second conductor portion, and resistivity of the first conductor portion of the first thin film transistor is greater than resistivity of the second conductor portion of the second thin film transistor.

THIN FILM TRANSISTOR, FABRICATION METHOD THEREOF, AND DISPLAY APPARATUS COMPRISING THE SAME
20230071089 · 2023-03-09 · ·

A thin film transistor includes an active layer including an oxide semiconductor layer, a metal layer disposed on the active layer and overlapping with at least a portion of the active layer, a gate electrode spaced apart from the active layer, and overlapping with at least a portion of the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes a channel portion, a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, and wherein the metal layer includes a first metal layer contacting an upper surface of the first connection portion, and a second metal layer contacting an upper surface of the second connection portion, a fabrication method of the thin film transistor, and a display apparatus comprising the same.

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
20230132252 · 2023-04-27 ·

A transistor substrate includes a substrate, a semiconductor layer overlapping the substrate, and a gate electrode overlapping the semiconductor layer. The semiconductor layer includes a channel unit, a conductive unit directly connected to an end of the channel unit, and an edge unit positioned at an edge of the conductive unit. A carbon concentration of the edge unit is higher than each of a carbon concentration of the channel unit and a carbon concentration of the conductive unit.

Display device including transistor and manufacturing method thereof

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Display device and production method for display device

A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.

Array substrate and method of manufacturing same

An array substrate and a method of manufacturing the same are provided. The array substrate includes an active island and a gate insulating layer, a gate, and an interlayer dielectric layer stacked on the active island. A color resist layer is disposed on the interlayer dielectric layer, and an orthographic projection of the color resist layer on a base substrate covers an orthographic projection of a channel region of the active island on the base substrate.

Display substrate and method for forming the same and display device

A display substrate, a method for forming the display substrate and a display device are provided. The display substrate includes: a first conductive pattern located on a base substrate, where a ring-shaped conductive protection structure is arranged at an edge of a preset region of the first conductive pattern and surrounds the preset region, and the conductive protection structure is made of an anti-dry-etching material; an insulation layer covering the first conductive pattern; and a second conductive pattern located on a side of the insulation layer away from the first conductive pattern, where the second conductive pattern is electrically connected to the first conductive pattern through the via-hole.

Active matrix substrate and method for manufacturing same

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

INTEGRATED LOGIC AND PASSIVE DEVICE STRUCTURE
20230065446 · 2023-03-02 ·

A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.

SEMICONDUCTOR STRUCTURE, METHOD OF FORMING STACKED UNIT LAYERS AND METHOD OF FORMING STACKED TWO-DIMENSIONAL MATERIAL LAYERS

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.