A display device includes: a display area including a plurality of pixels; a first peripheral area disposed at one side of the display area; and a second peripheral area disposed at the opposite side of the display area, wherein a first column spacer is disposed in the display area, a second column spacer is disposed in the first peripheral area, and a third column spacer is disposed in the second peripheral area. The patterns of an exposure mask utilized in the first peripheral area in which the second column spacer is disposed and the second peripheral area in which the third column spacer is disposed may be different from each other.

An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

A display device includes: a substrate; a first thin film transistor and a second thin film transistor arranged over the substrate; a display element connected to the first thin film transistor; a wiring connected to the second thin film transistor and including a first wiring layer and a second wiring layer; a pattern insulating layer arranged between the first wiring layer and the second wiring layer; a planarization layer covering the wiring; and a connection electrode arranged on the planarization layer and connected to the first wiring layer and the second wiring layer respectively through a first contact hole and a second contact hole.

A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

A thin film transistor including a substrate; a semiconductor layer disposed over the substrate; a gate insulting film disposed over the semiconductor layer; and a gate electrode. The semiconductor layer includes a channel region, a source region, and a drain region. The gate insulating film includes a first region and a second region. The second region borders the first region. The gate electrode is disposed over the first region. A step shape is formed where the second region meets the first region.

An array substrate manufacturing method, including: forming an active layer of a thin film transistor, in which photoresist with a partial thickness at a location corresponding to a channel area between source/drain electrodes of the thin film transistor on the active layer is reserved; forming a source/drain metal layer, and further forming source/drain electrodes; lifting off the photoresist with the partial thickness on the channel area between the source/drain electrodes. The array substrate manufacturing method can avoid damaging the metal oxide layer in the etching process for source/drain electrodes, and lower production cost, simplify processes, and increase yield and product profit.

A mask frame assembly for an electronic display device includes a frame, and a mask coupled to the frame, in which the mask includes a pattern hole defining a first area over which material may be deposited, and a dam surrounding the pattern hole and defining a second area smaller than the first area over which the material may be deposited. A method of manufacturing a mask frame assembly for an electronic display device is also disclosed.

In a method of manufacturing a transparent display device, a substrate including a pixel region and a transmission region may be provided. A first electrode may be formed on the substrate in the pixel region, and a display layer may be formed on the first electrode. A second electrode facing the first electrode may be formed on the display layer, and a capping structure including a first capping layer and a second capping layer may be formed on the second electrode. The first capping layer may be formed on the second electrode in the pixel region and a first region of the transmission region by using a mask that has an opening, the mask may be shifted, and the second capping layer may be formed on the second electrode in the pixel region and a second region of the transmission region by using the shifted mask.

A display module includes a thin film transistor (TFT) substrate including a class substrate and a TFT layer provided on a front surface of the glass substrate, the TFT layer including a TFT circuit, a plurality of light emitting diodes provided on the TFT layer, a plurality of first connection pads provided at a distance from each other on the front surface of the glass substrate and connected to the TFT circuit, a plurality of second connection pads provided at a distance from each other on a rear surface of the glass substrate and connected to a second circuit, where the second circuit is configured to supply power and is connected to a control board, and a plurality of side wirings electrically connecting each of the plurality of first connection pads to respective connection pads of the plurality of second connection pads.

An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.