An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield.

The present disclosure provides a method for producing a TFT array substrate, a TFT array substrate, and a display apparatus, and relates to a technical field of display. It can solve a problem of no signal transmission caused by fracture of a source signal line, without increasing a coupling capacitance of the TFT array substrate. The method for producing a TFT array substrate includes: forming a transparent conductive layer and a source-drain metal layer in sequence onto a base substrate; and patterning the source-drain metal layer and the transparent conductive layer in one patterning process to form a source signal line and a pixel electrode line overlapping with each other.

A fabrication method of a thin film transistor, a fabrication method of an array substrate, a display panel, and a display device are provided. The fabrication method of the thin film transistor comprises: forming a gate electrode, a gate insulating layer and an oxide active layer; forming an inverted trapezoidal dissolution layer whose cross section is inverted trapezoidal on the oxide active layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; forming a source/drain layer on the oxide active layer, the gate insulating layer and the inverted trapezoidal dissolution layer, a thickness of the inverted trapezoidal dissolution layer being greater than a thickness of the source/drain layer; and dissolving and removing the inverted trapezoidal dissolution layer with the organic solvent and removing the source/drain layer on the inverted trapezoidal dissolution layer, to form a source electrode and a drain electrode.

A method of manufacturing a display panel substrate having a semiconductor element includes a film forming step of forming a thin film, a resist film forming step of forming a positive resist film on the thin film, a first exposure step of selectively exposing a resist film via a photomask including a pattern of the semiconductor element, a second exposure step of selectively exposing the resist film by scanning and irradiating the resist film with light along an outline shape of the display panel substrate, a developing step of developing the resist film to remove the resist film exposed in the first and second exposure steps and form a resist pattern on the thin film, an etching step of etching the thin film using the resist pattern as a mask, and forming a thin-film pattern by selectively removing the thin film, and a peeling step of peeling the resist pattern.

The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.

The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: step 1, forming a gate (21) on a substrate (1); step 2, deposing a gate isolation layer (3); step 3, deposing an oxide semiconductor layer (4) and a first photoresistor layer (5); step 4, taking the gate (21) as a mask to implement a back side expose to the first photoresistor layer (5); step 5, forming an island shaped oxide semiconductor layer (41), and removing the island shaped first photoresistor layer (51); step 6, forming an island shaped etching stopper layer (6); step 7, forming a source/a drain; step 8, deposing a protecting layer (8), a second photoresistor layer (9), and implementing gray scal exposure, development to the second photoresistor layer (9); step 9, forming a pixel electrode via (81) to implement ashing process to the second photoresistor layer (9); step 10, deposing a pixel electrode layer (10); step 11, removing the remaining second photoresistor layer (9′), and forming a pixel electrode (10′); step 12, implementing anneal process.

An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises a display area and a non-display area that is outside the display area. The method comprises: forming a metal layer on a base substrate, the metal layer comprising a conductive pattern in the display area and a first electrode in the non-display area; forming a protective layer on the metal layer, a thickness of the protection layer in the non-display area being less than a thickness of the protection layer in the display area; forming a display electrode layer on the protection layer and removing the display electrode layer in the non-display area; and removing the protection layer in the non-display area.

A film patterning method is provided. The method comprises: performing a dry etching process on a film to be patterned, so as to form a patterned film; removing a suspended particle on the patterned film; and performing another dry etching process on the patterned film after the suspended particle is removed, to form a final pattern of the film. By moving or completely removing the suspended particle on the patterned film and then performing another dry etching process on the patterned film to etch away the etching residue, existence of the etching residue is completely avoided in the final pattern of the film, so that the product yield is improved and the product quality is ensured.

A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

The present disclosure provides an array substrate and fabricating method thereof, a display panel, and a display apparatus. A first active layer and common electrodes are formed on the substrate. A first gate insulating layer is formed on the first active layer. A gate electrode is formed on the first gate insulating layer. A second gate insulating layer is formed on he common electrodes and the gate electrode. Via-holes are formed in the second gate insulating layer to expose surface portions of the common electrodes. Source/drain electrodes are formed and electrically connected to the coma on electrodes through the via-holes. A second active layer and pixel electrodes are formed on the second gate insulating layer.