The present disclosure provides an array substrate, including a substrate, a first functional layer configured on one side of the substrate, a first insulating layer configured on the first functional layer facing away from the substrate, a second functional layer configured on the first insulating layer facing away from the substrate, a second insulating layer configured on the second functional layer facing away from the substrate, a third functional layer configured on the second insulating layer facing away from the substrate, a third insulating layer configured on the third functional layer facing away from the substrate, a fourth functional layer configured on the third insulating layer facing away from the substrate, and a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.

A display device may include a pixel circuit layer. A first electrode and a second electrode may be on the pixel circuit layer and spaced from each other. A first insulating layer may be on the pixel circuit layer, the first electrode, and the second electrode. A conductive pattern may be on the first insulating layer and electrically insulated from the first electrode and the second electrode. The bank may be on the conductive pattern. Light emitting elements may be located on the first insulating layer between the first electrode and the second electrode, and electrically coupled to the first electrode and the second electrode.

A thin film transistor array panel includes a substrate, a data line and a light blocking layer disposed on the substrate, a thin film transistor disposed on the light blocking layer and including a source electrode, a drain electrode, and an oxide semiconductor layer, and an insulating layer disposed on the substrate and including a first contact hole overlapping a portion of the data line, a second contact hole overlapping a portion of the source electrode, and a third contact hole overlapping a portion of the drain electrode, wherein the first contact hole, the second contact hole, and the third contact hole are arranged in a row in a first direction perpendicular to a direction in which the data line is extended.

According to one embodiment, a semiconductor device includes an insulating substrate including a pixel area and a peripheral circuit area around the pixel area, a first insulating layer which is provided on the insulating substrate and includes at least nitrogen, a second insulating layer at least provided on the first insulating layer of the peripheral circuit area, a first thin-film transistor which is provided above the first insulating layer of the pixel area and includes a first oxide semiconductor layer, and a second thin-film transistor which is provided on the second insulating layer of the peripheral circuit area and includes a second oxide semiconductor layer. The second insulating layer in the pixel area is thinner than that in the peripheral circuit area.

The present disclosure provides a method for manufacturing an array substrate, an array substrate and a display device. The method includes: forming a gate line, a gate electrode and an insulating layer which covers the gate line and the gate electrode on a first surface of a substrate; forming a semiconductive film on the insulating layer; patterning the semiconductive film using the gate electrode and the gate line as a mask, so as to form an source semiconductive layer at a region where the gate line and the gate electrode are located; and manufacturing a target semiconductive layer using the source semiconductive layer.

An array substrate is provided, wherein a pixel electrode has the same material as a source/drain and has a thickness less than that of the source/drain, or a common electrode has the same material as a gate and has a thickness less than that of the gate, which guarantees transmittance of the array substrate while reducing the process complexity. A display device and a manufacturing method of the array substrate are also provided.

A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.

A mask, including a transparent substrate and mask patterns formed on a surface of the transparent substrate, wherein the mask patterns include a first area for forming film patterns in a display area and a second area for forming film patterns in a non-display area; both the first area and the second area are provided with a plurality of patterned sub-masks; a distribution density of the patterned sub-masks in the first area is less than a distribution density of the patterned sub-masks in the second area; each patterned sub-mask includes a first pattern for forming a source electrode of a transistor, a second pattern for forming a drain electrode of the transistor, and a slit interposed between the first pattern and the second pattern; and a width of the slit in the first area is greater than a width of the slit in the second area.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.