Disclosed are a flexible array substrate, a preparation method thereof, and a flexible display panel. The flexible array substrate comprises a plurality of pixel island regions sequentially arranged, with a flexible region being disposed between adjacent pixel island regions, wherein each of the pixel island regions comprises a gate electrode, and the flexible region comprises a first connecting wire, an elastic layer disposed on the first connecting wire, and a second connecting wire disposed on the elastic layer, wherein a plurality of interlayer via holes are disposed in the elastic layer, an elastic conductive pillar is disposed in each of the interlayer via holes, the elastic conductive pillar is conductively connected to the first connecting wire and the second connecting wire respectively, and the first connecting wire and/or the second connecting wire are/is connected to the gate electrodes of adjacent pixel island regions.

The present disclosure provides an array substrate, a method for preparing the same, and a display device. The method includes: forming a metal layer on a base substrate; coating a photoresist on the metal layer; exposing the photoresist by a mask plate in such a manner that an amount of light acting on a first photoresist portion is less than that of light acting on a second photoresist portion to form a first photoresist reserved portion located and a second photoresist reserved portion located; after etching off the metal portion, stripping the first photoresist reserved portion and the second photoresist reserved portion, to obtain the first metal pattern located in the fan-out area and the second metal pattern located in the display area, in which a period size of the first metal pattern being smaller than a period size of the second metal pattern.

An array substrate is provided, including a base substrate, a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode that are sequentially provided, and further including a first insulating layer, a second insulating layer, a third insulating layer, at least one first via, and at least one second via. Each first via penetrates through the third insulating layer, and in each pixel unit with plural chromatic color resists, each first via is between adjacent two chromatic color resists and filled by one of the adjacent two chromatic color resists. Each second via penetrates through the second insulating layer, the at least one second via is in one-to-one correspondence with the at least one first via, each second via is filled by a chromatic color resist having a same color as that of the chromatic color resist in the corresponding first via.

A method of manufacturing an array substrate, includes: providing a substrate; forming a gate conductive layer including at least one first alignment mark; forming a source-drain conductive thin film; aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark; patterning the source-drain conductive thin film by using the first mask to form at least one second alignment mark to obtain a source-drain conductive layer; forming a black matrix thin film; aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark; patterning the black matrix thin film by using the second mask to form a black matrix; and forming a color filter layer.

A display panel and a method of manufacturing the same are provided. The display panel includes a shielding layer, a thin film transistor device layer, and a first via hole and a second via hole disposed correspondingly, and a third via hole disposed in a bonding area. Specifically, each of the first via hole and the third via hole is a stair-step shaped hole. The first via hole, the second via hole, and the third via hole are etched through a same etching process. Only one-time mask process is required, which saves number of masks and lowers the production cost.

A display device is provided. The display device comprising: a substrate including a display area and a pad area, a first conductive layer disposed on the substrate and including a first signal line disposed in the display area, a buffer layer disposed on the first conductive layer, a semiconductor layer disposed on the buffer layer in the display area, a gate insulating film disposed on the semiconductor layer, a second conductive layer disposed on the gate insulating film and including a gate electrode overlapping the semiconductor layer in the display area, a first electrode of a transistor disposed to overlap one side of the semiconductor layer in the display area and connected to the first signal line through a contact hole penetrating through the buffer layer and the gate insulating film, and a second electrode of the transistor disposed to overlap the other side of the semiconductor layer in the display area, a first pad disposed on the buffer layer in the pad area and exposed by a pad opening, a first insulating layer disposed on the second conductive layer and the first pad, and a light emitting element disposed on the first insulating layer in the display area, wherein the first pad is formed of the first conductive layer or the second conductive layer.

A manufacturing method of an array substrate and a display panel are disclosed. The manufacturing method includes: disposing a photoresist on an active switch; disposing a protective layer on the active switch; disposing a pixel electrode layer on the protective layer. The step of etching each film layer material based on the photoresist to form an active switch includes: performing a first wet etching on the active switch; performing a first dry etching and two ashing treatments on the active switch; performing a second wet etching on the active switch; and removing the photoresist. The present application can improve the issue of photoresist residues.

A display device includes a conductive pattern on a substrate, a via layer on the conductive pattern with a via hole exposing the conductive pattern, a first electrode and a second electrode on the via layer and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, a bank layer on the first insulating layer defining an emission area and a subarea, a light-emitting element on the first insulating layer, and a first connection electrode and a second connection electrode on the first insulating layer and the light-emitting element. The first connection electrode electrically contacts an end of the light-emitting element, and the second connection electrode electrically contacts another end of the light-emitting element. The bank layer includes a bank extension portion extended to the subarea and the bank extension portion overlaps at least a portion of the via hole.

A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

A display apparatus comprises a first signal line on a substrate, a second signal line intersecting with the first signal line, a first gate electrode, a first source electrode, a first drain electrode, and a second gate electrode disposed on the same layer as that of the first signal line, a first active layer spaced apart from the first gate electrode and partially overlapped with the first gate electrode, a second active layer spaced apart from the second gate electrode and partially overlapped with the second gate electrode, and a first electrode of a display device connected with the second active layer.