An imaging device according to an embodiment of the present disclosure includes: a first substrate; a second substrate; and a through wiring line. The first substrate includes a photoelectric conversion section and a first transistor in a first semiconductor substrate. The photoelectric conversion section and the first transistor are included in a sensor pixel. The second substrate is stacked on the first substrate and includes a second transistor and an opening that extends through a second semiconductor substrate. The second substrate has an adjuster on at least one of a side surface of the opening near a gate of the second transistor or a region of a surface opposed to the first transistor. The second transistor is included in the sensor pixel. The adjuster adjusts a threshold voltage of the second transistor. The through wiring line is in the opening and electrically couples the first substrate and the second substrate.

Provided are a semiconductor device capable of reducing a substrate bias effect, and an imaging device using the semiconductor device. The semiconductor device includes a semiconductor substrate, and a field effect transistor provided on a first main surface of the semiconductor substrate. The field effect transistor includes a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, a gate insulating film disposed between the semiconductor region and the gate electrode, and a first insulating film disposed between the semiconductor region and the semiconductor substrate. The semiconductor region has an upper surface, a first side surface located on one side of the upper surface in a first direction parallel to the upper surface, and a second side surface located on the other side of the upper surface in the first direction. The gate electrode has a first portion facing the upper surface with the gate insulating film interposed therebetween, a second portion facing the first side surface with the gate insulating film interposed therebetween, and a third portion facing the second side surface with the gate insulating film interposed therebetween.

A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.

A pixel circuit of a photoelectric conversion device includes two photoelectric conversion elements, each including two impurity region in each of two different layers. In at least one pixel of the pixel circuits, a first separation region separating the two impurity regions in a first layer and a second separation region separating the two impurity regions in a second layer extend in directions different from each other in a planer view. An impurity region in a photoelectric conversion element includes a first portion overlapping the first separation region in the planar view, a second portion adjacent to a first transfer gate, and a third portion located on an opposite side of the second portion with respect to the first portion. The impurity region has a potential distribution monotonically decreasing from the third portion to the second portion for signal charges.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

A shallow trench isolation (STI) structure and method of fabrication includes forming a shallow trench isolation (STI) structure having a polygonal shaped cross-section in a semiconductor substrate of an image sensor includes a two-step etching process. The first step is a dry plasma etch that forms a portion of the trench to a first depth. The second step is a wet etch process that completes the trench etching to the desired depth and cures damage caused by the dry etch process. A CMOS image sensor includes a semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation (STI) structure having a polygonal shaped cross-section.

The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The device includes a photoelectric conversion section; a trench between the photoelectric conversion sections in adjacent pixels; and a PN junction region on a sidewall of the trench and including a P-type region and an N-type region, the P-type region having a protruding region. The device can include an inorganic photoelectric conversion section having a pn junction and an organic photoelectric conversion section having an organic photoelectric conversion film that are stacked in a depth direction within a same pixel; and a PN junction region on a sidewall of the inorganic photoelectric conversion section. The PN junction region can further include a first P-type region and an N-type region; and a second P-type region. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.

A photo detector having a substrate and a first structure formed on the substrate. The first structure includes an emitter layer formed on the substrate and a base layer formed on the emitter layer. Further, the first structure includes a collector layer formed on the base layer. The collector layer has a plasmonic structure. The plasmonic structure includes a first plurality of mesa structures. Each of the mesa structures of the first plurality of mesa structures includes a second plurality of mesa structures having ridges arranged in a regularly repeating pattern.

The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

An image sensor includes a substrate having a first surface and a second surface facing each other, a plurality of photoelectric conversion regions disposed in the substrate, an isolation pattern disposed in the substrate between the photoelectric conversion regions, a conductive connection pattern disposed on the isolation pattern and in a trench penetrating the first surface of the substrate, and a first impurity region disposed in the substrate and adjacent to the first surface of the substrate. A first sidewall of the conductive connection pattern is in contact with the first impurity region. A dopant included in the conductive connection pattern includes the same element as an impurity doped in the first impurity region.