A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.

A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

An imaging sensor array comprises an epitaxial germanium layer disposed on a silicon layer, and an electrically biased photoelectron collector arranged on the silicon layer, on a side opposite the germanium layer.

To prevent peeling at an interface between layers forming a layer structure of a solid-state imaging element even in a case where stress is caused by an increase in pressure in a cavity in a configuration in which a translucent member is provided on the solid-state imaging element with a support portion interposed therebetween and the cavity is formed between the solid-state imaging element and the translucent member. There are included a solid-state imaging element, the light-receiving side of which corresponds to one of plate surface sides of a semiconductor substrate; a translucent member provided on the light-receiving side of the solid-state imaging element at a predetermined distance therefrom; and a support portion that forms a cavity between the solid-state imaging element and the translucent member, in which the solid-state imaging element has a layer structure provided on the light-receiving side of the semiconductor substrate, the layer structure including a first layer, a second layer, and a third layer, the second layer being different in material from the first layer, the third layer being different in material from the first layer and formed in the second layer, and the third layer has a protrusion-and-recess shape portion at least in a region where the support portion is formed in a planar direction along the plate surface of the semiconductor substrate, the protrusion-and-recess shape portion forming an interface between the second layer and the third layer in a protrusion-and-recess shape.

An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided.

A method includes preparing an electronic component that includes an element plate including an element region provided with a functional element and a peripheral region disposed around the element region, a counter plate facing the element region and the peripheral region, a first resin member disposed between at least one of the element region and the peripheral region and the counter plate, and a second resin member disposed between the peripheral region and the counter plate, applying light to the element plate through the counter plate and the second resin member, and measuring a gap between the counter plate and the element plate based on light reflected between the element plate and the second resin member and light reflected between the counter plate and the second resin member.

A method for manufacturing an image sensor includes, for each of a plurality of photosensitive pixels of the image sensor, forming a trench in a semiconductor substrate of the image sensor, and depositing temporary transfer gate material in and above the trench. The method further includes, after the step of depositing temporary transfer gate material, high-temperature annealing at least a portion of the semiconductor substrate. In addition, the method includes, after the step of high-temperature annealing, (a) removing the temporary transfer gate material, thereby reopening the trench, (b) depositing a passivation lining, having a high-k dielectric, in the reopened trench, and (c) depositing metal on the high-k dielectric passivation lining to form a metal vertical transfer gate in the trench and extending above the trench.

A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of isolation structures are each disposed between two respective radiation-sensing regions. The isolation structures protrude out of the second side of the substrate.

Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.