The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n.sup. type drift region and not penetrating a SiC substrate; an n.sup.+ type side surface diffusion region formed on each side surface of the first trench; an n.sup.+ type bottom diffusion region formed under the n.sup. type drift region and in contact with the n.sup.+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n.sup. type drift region at regular spacings of 0.4 m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.

A electrical switch has a first substrate, a first conducting layer disposed on the first substrate, a first dielectric layer disposed on the first conducting layer and a second conducting layer disposed on the first dielectric layer, and the second conducting layer disposed on the second substrate, and a conductive via connected to the first conducting layer and extending through the first dielectric layer. Active dielectric has a first conductor, a first dielectric layer disposed on the first conducting layer, one or more electrical switches disposed on the first dielectric layer, a dielectric layer disposed between neighboring electrical switches, the second dielectric layer disposed on the last electrical switch, and the second conducting layer disposed on the second dielectric layer.

A p anode layer is formed on one main surface of an n.sup. drift layer. N.sup.+ cathode layer having an impurity concentration more than that of the n.sup. drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n.sup.+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n.sup.+ cathode layer and p anode layer is formed in the n.sup. drift layer. Resistivity .sub.0 of the n.sup. drift layer satisfies 0.12V.sub.0.sub.00.25V.sub.0 with respect to rated voltage V.sub.0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.810.sup.11 atoms/cm.sup.2 and equal to or less than 1.010.sup.12 atoms/cm.sup.2.

A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.

Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.

A semiconductor device includes a semiconductor substrate, a trench provided in the semiconductor substrate, a trench gate formed in the trench, a vertical transistor having the trench gate, an active region having the vertical transistor, a field region surrounding the active region and having a protection diode, and a field insulating film formed on a surface of the semiconductor substrate, the protection diode being formed on the field insulating film. The trench gate includes a first polysilicon layer and has an embedded part embedded in the trench and an extension part connected to the embedded part and extending onto the surface of the semiconductor substrate, the protection diode includes a second polysilicon layer thicker than the first polysilicon layer, and an overlapping part having the second polysilicon layer is formed on the extension part.

A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.

An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced.