Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

The embodiments of the invention provides a semiconductor device and a method for manufacturing it The semiconductor device provided by the embodiments of the invention comprises: a first electrode layer; a substrate layer positioned on the first electrode layer; an epitaxy layer positioned on the substrate layer and comprising a first surface far from the substrate layer; a plurality of well regions disposed by extending from the first surface into the epitaxy layer and orthographic projections thereof on the first surface are spaced from each other; a second electrode layer, comprising first metal layers, each disposed between adjacent two of the well regions on the first surface and forms a Schottky contact with the epitaxy layer, wherein the Schottky contact has variable barrier height. The semiconductor device provided by the embodiments of the invention may improve the forward conduction ability without affecting the reverse blocking ability.

A gate electrode structure and a high voltage semiconductor device having the same are disclosed. The gate electrode structure includes a gate insulation layer pattern disposed on a substrate, a gate electrode disposed on the gate insulating layer pattern and having at least one opening at a first side portion thereof, and at least one insulating pattern disposed in the at least one opening. The high voltage semiconductor device includes a drift region disposed in the substrate adjacent to the first side portion of the gate electrode, a drain region electrically connected with the drift region, and a source region disposed in the substrate adjacent to a second side portion of the gate electrode.

In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.

Provided is a semiconductor device including a semiconductor substrate having a drift region; a transistor portion having a collector region; a diode portion having a cathode region; and a boundary portion arranged between the transistor portion and the diode portion at an upper surface of the semiconductor substrate, and having the collector region, wherein the mesa portion of each of the transistor portion and the boundary portion has an emitter region and a base region, the base region has a channel portion, and a density in the upper surface of the mesa portion in the region in which the channel portion is projected onto the upper surface of the mesa portion of the boundary portion may be smaller than the density of the region in which the channel portion is projected onto the upper surface of the mesa portion of the transistor portion.

Disclosed are a bidirectional power device and a method for manufacturing the same. The bidirectional power device includes a semiconductor layer, a plurality of trenches located in the semiconductor layer, a gate dielectric layer located on an inner wall of each of the plurality of trenches, a control gate located at a lower portion of each of the plurality of trenches, a shield gate located at an upper portion of each of the plurality of trenches and an isolation layer located between the control gate and the shield gate. When the bidirectional power device is turned off, charges of a source region and a drain region are depleted by the shield gate through a shield dielectric layer, thereby improving voltage withstand property. When the bidirectional power device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.

A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region.

The device electrode is located in a device trench in the active region, and is electrically isolated from the epitaxial layer and the contact metal layer. The first termination electrode is located in a first termination trench in the termination region and is electrically isolated from the epitaxial layer. The second termination electrode is located at a bottom of the first termination trench and is electrically isolated from the first termination electrode and the epitaxial layer. Both the first termination electrode and the second termination electrode are capable of being selectively floating.