A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.

High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

A semiconductor device includes first and second layers and first and second electrodes. The first layer has a first semiconductor containing an impurity of a first conductivity type. The second layer is in contact with the first layer and has a second semiconductor containing the impurity at a lower concentration than the first semiconductor. The first electrode is in contact with a first surface of the first layer. The second electrode is in contact with a second surface of the second layer. The second layer further has first and second trenches. The first trench has therein a third electrode connected to the second electrode. The second trench is located closer to an outer perimeter portion of the second layer than the first trench and has therein a fourth electrode connected to the second electrode. An entire outer perimeter end of the second electrode is in contact with the fourth electrode.

An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.

A semiconductor device includes first to fourth electrodes, a semiconductor portion, and first and second insulating films. The semiconductor portion includes first to third semiconductor layers. The second electrode is in contact with the third semiconductor layer and is spaced from the second semiconductor layer, the third semiconductor layer, and the second electrode. The first insulating film covers the third electrode. The fourth electrode is connected to the second electrode, and is spaced from the first semiconductor layer and the third electrode. The second insulating film is provided on a side surface of the fourth electrode, faces the first semiconductor layer through an air gap, and increases in thickness toward the first direction.

Diodes, transistors, and other devices having a class IV channel region and a class III-V drift region are described. The class IV channel region, such as a Si channel region, is able to provide all associated advantages, such as ease of manufacturing of many different types of devices, using cost-effective materials and techniques. Meanwhile, the III-V drift region provides substantially lower R.sub.on_sp than a conventional class IV drift region, and substantially enhances the operational behaviors of resulting devices, without sacrificing other parameters, such as size or breakdown voltage.

The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor.

The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.

The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.