In an edge termination region, a FLR structure configured by FLRs having a floating potential and surrounding concentrically a periphery of an active region is provided. The FLR structure is divided into at least two FLR segments with a predetermined FLR as a boundary. An n-th interval between an adjacent two of the FLRs is wider than a first interval between a p.sup.+-type extension portion and the FLR closest to a chip center (n=2 to total number of the FLRs). The n-th interval between an adjacent two of the FLRs increases in arithmetic progression the closer the adjacent two are to a chip end, the n-th interval increasing in arithmetic progression by a corresponding one of constant increase increments respectively corresponding to the FLR segments; the closer a FLR segment is to the chip end, the wider is the constant increase increment corresponding thereto.

Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

A FLR structure is provided in an edge termination region as a voltage withstanding structure. The FLR structure is configured by multiple FLRs that concentrically surround a periphery of an active region. An impurity concentration of the FLRs is less than 1×10.sup.18/cm.sup.3 or preferably, may be in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A thickness of each of the FLRs is in a range of 0.7 μm to 1.1 μm. A first interval between an innermost FLR and an outer peripheral pt-type region is at most about 1.2 μm.

Provided in the present disclosure are an IGBT device backside structure and a preparation method therefor, and an IGBT device, the IGBT device backside structure comprising a buffer layer, the buffer layer comprising a first activation efficiency buffer area corresponding to an active area of the IGBT device and a second activation efficiency buffer area corresponding to a terminal area of the IGBT device, the activation efficiency of the first activation efficiency buffer area being less than the activation efficiency of the second activation efficiency buffer area.

Provided is a semiconductor device including a semiconductor substrate having a first dopant of a first conductivity type and a second dopant of a second conductivity type, both the first dopant and the second dopant being distributed in an entire part of the semiconductor substrate, the semiconductor substrate including a drift region of the first conductivity type, a dielectric film provided on an upper surface of the semiconductor substrate, a high concentration region of the first conductivity type provided in contact with the dielectric film below the dielectric film and having a higher doping concentration than the drift region, and a fall off region that is provided in contact with the dielectric film below the dielectric film and in which a concentration of the dopant of the second conductivity type decreases toward the dielectric film.

A semiconductor device includes a semiconductor part, first and second electrodes and a control electrode. The semiconductor part is provided between the first and second electrode. The semiconductor part includes first and third layers of a first conductivity type, and second, fourth and fifth layers of a second conductivity type. The first layer extends between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third semiconductor layer is provided between the second layer and the second electrode. The fourth layer is provided between the first layer and the first electrode. The semiconductor part includes an active region and a termination region. The active region includes the control electrode, the second layer, and the third layer. The termination region surrounds the active region.

The fifth layer is provided in the first layer in the termination region.

Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; an active portion, in which at least one of a transistor portion and a diode portion is provided, in the semiconductor substrate; and an edge termination structure portion provided farther outward than the active portion in the semiconductor substrate, wherein the edge termination structure portion has a plurality of guard rings of a second conductivity type provided in contact with an upper surface of the semiconductor substrate, and an embedded dielectric film arranged between two guard rings and at least partially embedded in the semiconductor substrate, and the guard rings are provided up to a position below the embedded dielectric film.

A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.

FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Current concentration in a channel region is reduced in a case where diffusion occurs of impurities from an element isolation region. A semiconductor element includes the element isolation region formed on a semiconductor substrate, a source region, a drain region, a gate, and the channel region. The gate is arranged on a surface of the semiconductor substrate between the source region and the drain region with an insulating film interposed between the gate and the semiconductor substrate. The channel region is arranged directly below the gate and between the source region and the drain region and is arranged adjacent to the element isolation region, and has a shape in which a channel length that is a distance between the drain region and the source region is shortened in the vicinity of the element isolation region.