The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.

A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A light sensitive semiconductor structure including a pn-junction in a silicon substrate. The pn-junction includes a central part and an edge part around surrounding the central part, the edge part being in contact with a surface of the silicon substrate. The structure further includes a plasma shielding structure covering at least a depletion width of the pn-junction over at least a part of the edge part where the edge part contacts the surface of the silicon substrate.

Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.