An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.

A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.

A process of forming a nitride semiconductor device is disclosed. The process includes s steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO.sub.2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO.sub.2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region selectively within the recess simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film by removing the SiO.sub.2 film and the second SiN film.

A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer with a thick portion positioned laterally between thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between thin portions. The gate also includes a gate conductor layer on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.

According to one embodiment, a semiconductor device include first to third electrode, a semiconductor member, a first conductive member, and a first insulating member. A second insulating region of the first insulating member includes a first face facing the third partial region of the first semiconductor region. The third insulating region of the first insulating member includes a second face facing the third partial region of the first semiconductor region. The first face includes a first end on a side of the first electrode in the first direction. The second face includes a second end on a side of the second electrode in the first direction. A second position of the second end in the second direction is different from a first position of the first end in the second direction.

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes a gate layer formed on an electron supply layer; a first insulating film, formed on the gate layer and having an opening exposing the gate layer; and a gate electrode including a gate field plate portion formed on the first insulating film. A side surface of the first insulating film is located further inside the gate electrode than a side surface of the gate field plate portion. The nitride semiconductor device further includes a second insulating film covering at least side surfaces of each of the gate layer, the first insulating film and the gate electrode. The second insulating film includes a portion embedded in a recessed portion formed by a lower surface of the gate field plate portion, the side surface of the first insulating film and an upper surface of the gate layer.