An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

The present disclosure relates to four-layer latching devices having improved reverse current capabilities. The devices have a localized doping spike region in the upper base region, the lower base region, or both. The localized doping spike regions have a localized doping concentration that is greater than the doping concentration of the layer where the localized doping spike region is located. Within the base regions the localized spikes are located next to the corresponding upper emitter region, lower emitter region, or both.

A power semiconductor device (1) comprises a gate-commutated thyristor cell (20) including a cathode electrode (2), a cathode region (9) of a first conductivity type, a base layer (8) of a second conductivity type, a drift layer (7) of the first conductivity type, an anode layer (5) of the second conductivity type, an anode electrode (3) and a gate electrode (4). The base layer (8) comprises a cathode base region (81) located between the cathode region (9) and the drift layer (7) and having a first depth (D1), a gate base region (82) located between the gate electrode (4) and the drift layer (7) and having a second depth (D2), and an intermediate base region (83) located between the cathode base region (81) and the gate base region (82) and having two different values of a third depth (D3) being between the first depth (D1) and the second depth (D2).

Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled for an operation on a set of memory cells in an array, sequentially engaging subsets of memory cells for the operation while keeping the remaining memory cells of the set on hold until all the memory cells of the set have been operated on.

A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

A silicon controlled rectifier includes a first P region, an N? region, a second P region, and a plurality of N+ regions. The first P region is connected to an anode. The N? region is adjacent the first P region. The second P region is adjacent the N? region such that the N? region is sandwiched between the first P region and the second P region. The plurality of N+ regions are disposed within the second P region. A first N+ region of the plurality of N+ regions is connected to a cathode. A second N+ region of the plurality of N+ regions is connected to a gate.

An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ceb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (<250 ns). Additionally, series resistance of the device is reduced without comprising voltage blocking ability is achieved. Finally, a positive only gate drive means is taught as is a method to module the saturation current using the gate terminal.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gate structure.