A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a source, a drain, a gate structure, and a first p-type doped III-V compound/nitride semiconductor layer. The second semiconductor layer is disposed on the first semiconductor layer and has a bandgap greater than a bandgap of the first semiconductor layer. The source and the drain are disposed on the second semiconductor layer. The gate structure is disposed on the second semiconductor layer and between the source and the drain. The first p-type doped III-V/nitride semiconductor compound layer is disposed on the second semiconductor layer and between the gate structure and the drain with the drain at least partially covering the p-doped layer such that the first p-type doped III-V compound/nitride semiconductor layer and the drain are electrically coupled with each other.

A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.

The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein at least one of a vertical two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.

Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

A method for fabricating a semiconductor device including vertical transistors having uniform channel length includes defining a channel length of at least one first fin formed on a substrate in a first device region and a channel length of at least one second fin formed on the substrate in a second device region. Defining the channel lengths includes creating at least one divot in the second device region. The method further includes modifying the channel length of the at least one second fin to be substantially similar to the channel length of the at least one first fin by filling the at least one divot with additional gate conductor material.

A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.

A device and method of fabricating a device having depletion-mode and enhancement-mode high-electron-mobility transistors (HEMTs) on a single wafer are disclosed. The method of fabrication involves providing semiconductor layers capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT, forming a series of trenches and fins in the semiconductor layers over an active area of the semiconductor layers on which a gate contact terminal is to be set down, the fins of respective HEMTs having different widths resulting in different voltage thresholds for the respective depletion-mode HEMTs.

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.