A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate; forming a support layer at least partially on sidewalls of the fins; ion implanting the fins through the support layer to form an ion doped region by an ion implantation process; removing the support layer to expose sidewalls of the fins.

A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.

An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

A device includes a particle propagation channel, a particle deflector, a particle source, and a particle sink. The particle deflector facilitates ballistic transport of particles from a particle inflow portion through a particle flow deflection portion to a particle outflow portion. The particle deflector is arranged at the particle flow deflection portion and is activatable to deflect particles in the flow deflection portion and is configured to selectively prevent the particles from reaching the particle outflow portion. The particle source and particle sink are configured to cause a current path of the particles through the device.

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.