An InGaAlP Schottky field effect transistor with AlGaAs carrier supply layer comprises a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer and a cap layer sequentially formed on a compound semiconductor substrate; the cap layer has a gate recess, a bottom of the gate recess is defined by the Schottky barrier layer; a source electrode and a drain electrode are formed respectively on the cap layer at two sides with respect to the gate recess, the source electrode and the drain electrode form respectively an ohmic contact with the cap layer; a gate electrode is formed on the Schottky barrier layer within the gate recess, the gate electrode and the Schottky barrier layer form a Schottky contact; wherein the carrier supply layer is made of AlGaAs; the Schottky barrier layer is made of InGaAlP.

The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; and a channel region under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.

A compound semiconductor substrate having a desired quality is provided. A compound semiconductor substrate has an SiC (silicon carbide) layer, an AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a first GaN (gallium nitride) layer formed on the Al nitride semiconductor layer, a first AlN intermediate layer formed on the first GaN layer in contact with the first GaN layer, and a second GaN layer formed on the first AlN intermediate layer in contact with the first AlN intermediate layer.

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

A disclosed compound semiconductor device includes a channel layer configured to generate carriers; a spacer layer of Al.sub.y1Ga.sub.1-y1N (0.20<y10.70) formed on the channel layer; and a barrier layer of In.sub.x2Al.sub.y2 Ga.sub.1-x2-y2N (0x20.15 and 0.20y2<0.70) formed on the spacer layer, where y1 and y2 satisfy a relationship of y1>y2.

Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 110.sup.6 .Math.cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 110.sup.17/cm.sup.3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1, 0y1).

Low-power multi-stage amplifiers are provided for capacitive reading of low-amplitude and low-frequency signals. An exemplary multi-stage amplifier comprises a plurality of amplification stages, wherein each of the amplification stages comprises an amplifying transistor and an active load, wherein substantially all of the amplification stages have one or more of an increasing DC bias level and a decreasing DC bias level relative to a prior stage, and wherein an output of a given one of the amplification stages is directly applied as an input to a subsequent one of the amplification stages.

An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

A method for manufacturing a semiconductor device includes patterning a strained semiconductor layer on a substrate into at least one strained fin, forming a plurality of dummy gates spaced apart from each other on the at least one strained fin, forming a spacer layer on the plurality of dummy gates, and on part of the at least one strained fin between the plurality of dummy gates, growing a plurality of source/drain regions on exposed portions of the at least one strained fin, removing the spacer layer from the part of the at least one strained fin between the plurality of dummy gates, and converting the part of the at least one strained fin between the plurality of dummy gates into at least one oxide.