An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of Al.sub.xGa.sub.(1-x)N, Al.sub.yGa.sub.(1-y)N, and Al.sub.zGa.sub.(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

A lateral GaN superjunction transistor or switching device that is configured to have higher breakdown voltage and lower on-resistance as compared to other GaN-based switching devices. The lateral GaN superjunction transistor includes a heavily doped buried implant region (hereinafter, “buried implant region”) in the substrate underlying the transistor that operates as backside field plate (BFP) to control or reduce gate-drain electric fields at the surface of the transistor, thereby enabling the transistor to operate at higher voltages while reducing charge trapping and breakdown effects. The lateral GaN superjunction transistor operates similarly to a vertical silicon superjunction FET to enable operation of the transistor at higher voltages than other GaN or semiconductor devices, such as to enable the construction of faster or higher power electronic circuits.

The invention relates to a semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises Al.sub.zGa.sub.1-zN and wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity, and wherein the gate layer comprises any of GaN and/or Al.sub.uIn.sub.vGa.sub.1-v-uN. A field effect transistor according to the disclosure may be configured to show a gate threshold voltage which is higher than approximately 0.5 V or higher than approximately 1.0 V.

A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.

Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a field-effect transistor (FET) can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the field-effect transistor.

A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.