Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having increased collector thickness for improved ruggedness. In some embodiments, the collector thickness can be above 1.1 microns. The collector can have at least one doping concentration grading. The collector can have a high doping concentration at a junction between the collector and the sub-collector, such as at the high end of the grading. In some embodiments, the high doping concentration can be above about 9×10.sup.16 cm.sup.−3. The collector can include a region with high doping concentration adjacent the base. The collector can include a discontinuity in the doping concentration, such as at the low end of the grading. Such bipolar transistors can be implemented, for example, in power amplifiers.

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.