A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN, where x≤1 and y≥0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN, where x≤1 and y≥0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.