A semiconductor device and a method of manufacturing thereof are provided. The semiconductor device comprises a gate stack, source/drain regions, and a source/drain contact via. The gate stack is disposed on a substrate. The source/drain regions are disposed on the substrate and located at opposite sides of the gate stack. The source/drain contact via penetrates through the substrate and is electrically connected to a first source/drain region among the source/drain regions. The source/drain contact vias comprise a first conductor and a second conductor disposed on the first conductor. The first conductor comprises a silicide layer and a first metallic portion. The second conductor comprises a glue layer and a second metallic portion. The first metallic portion is spaced apart from the second metallic portion by the glue layer.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Disclosed are a preparation method for a diamond-based field effect transistor and a field effect transistor, relating to the technical field of semi-conductors. Said method comprising: forming a conductive layer on the upper surface of a diamond layer; the diamond layer being a high-resistance layer; manufacturing an active region mesa on the diamond layer; manufacturing, on the conductive layer, a source electrode on a first region corresponding to a source electrode region, and manufacturing, on the conductive layer, a drain electrode on a second region corresponding to a drain electrode region; depositing, on the conductive layer, a photocatalyst dielectric layer on the upper surface of a third region corresponding to a source and gate region, and depositing, on the conductive layer, the photocatalyst dielectric layer on the upper surface of a fourth region corresponding to a gate and drain region; illuminating the photocatalyst dielectric layer; depositing, on the conductive layer, a gate dielectric layer on a fifth region corresponding to gate electrode region, manufacturing a gate electrode on the upper surface of the gate dielectric layer. The present invention can reduce the on-resistance of devices.

A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Precision and chip contamination-free placement of two-dimensional (2D) material and van der Waals (VDW) layered materials accelerates both the study of fundamental properties and novel device functionality. The system transfers 2D materials utilizing a combination of a narrow transfer-stamper and viscoelastic and optically transparent film. Precise placement of individual 2D materials results in vanishing cross-contamination to the substrate. The 2D printer results in an aerial cross-contamination improvement of two to three orders of magnitude relative to state-of-the-art transfer methods from a source of average area sub um{circumflex over ()}2. The transfer-stamper does not physically harm any micro/nanostructures preexisting on the target substrates receiving the 2D material such as, nanoelectronics, waveguides or micro-ring resonators. Such accurate and substrate-benign transfer method for 2D and VDW layered materials provides rapid device prototyping due to its high time-reduction, accuracy, and contamination-free process.

According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.

The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Disclosed herein is a method of fabricating hexagonal boron nitride in which hexagonal boron nitride is epitaxially grown. A method of fabricating hexagonal boron nitride includes placing a catalytic metal in a chamber, the catalytic metal having a hexagonal crystal structure and having a lattice mismatch of 15% or less with hexagonal boron nitride (h-BN) in a chamber; and growing hexagonal boron nitride on the catalytic metal at a temperature of 800 C. or lower while supplying a nitrogen source and a boron source into the chamber.

Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.