Disclosed is a field effect transistor (FET) and a method for manufacturing the same, the FET comprises: a substrate, a first well region located on the substrate, a second well region, a body contact region, a source region, a drain region and a gate conductor. The body contact region, the source region and the drain region are located in the first well region, the doping concentration of the second well region is higher than that of the first well region. A parasitic bipolar junction transistor (BJT) is located in the field effect transistor, current flowing through the BJT is controlled by adjusting doping concentration or area of the second well region. The second well region is formed in the first well region, so that the holding voltage of the FET is improved, and finally effect on the FET caused by the current flowing through the BJT can be weakened.

An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

We herein describe a method of manufacturing a semiconductor device having one or more trenches with an insulation layer. The one or more trenches with an insulation layer are manufactured using the steps of performing an etching process to form the one or more trenches, forming a first insulation layer on a lower surface and sidewalls of the one or more trenches, depositing a hydrophilic layer over the first insulation layer, depositing a photoresist material in the one or more trenches, wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of a first side of the one or more trenches, performing a wet etch process to etch the insulation layer on the sidewall of the first side of the one or more trenches to a predetermined distance below a surface of the photoresist material, removing the photoresist material, removing the hydrophilic layer, and after performing the wet etch process, removing the photoresist material, and removing the hydrophilic layer, and forming a second insulation layer on the sidewall of the first side of the one or more trenches.

Provided are a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; and a stressor adjacent to the 2D material electrode bonding layer. The stressor may be configured to apply a tensile strain to the 2D material electrode bonding layer.

By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

Semiconductor devices having improved electrical characteristics are described, as are methods of fabricating the same. The semiconductor device may include a first gate electrode on a substrate and extending in a first direction, a second gate electrode on the substrate and running across the first gate electrode while extending in a second direction, and a channel structure between the second gate electrode and lateral surfaces in the second direction of the first gate electrode and between the second gate electrode and a top surface of the first gate electrode. The channel structure may include a first dielectric layer that covers in contact with the lateral surfaces and the top surface of the first gate electrode; a second dielectric layer on the first dielectric layer and in contact with the second gate electrode; and a channel layer between the first dielectric layer and the second dielectric layer.

The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer. The semiconductor device includes a first semiconductor layer of a first conductivity type which is either a p-type or an n-type conductivity type, a source portion arranged so as to be in contact with the first semiconductor layer and configured as a semiconductor portion of a second conductivity type different from the first conductivity type, a source electrode arranged in ohmic contact with the source portion, a gate electrode arranged on at least one selected from surfaces of the first semiconductor layer via a gate insulating film interposed therebetween and capable of forming by an applied electric field, an inversion layer in a region of the first semiconductor layer near the surface of the first semiconductor layer contacting the gate insulating film, a second semiconductor layer of the first conductivity type arranged so as to be in contact with the inversion layer, and a drain electrode separated from the inversion layer and arranged in Schottky contact with the second semiconductor layer.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.