The technique disclosed in the Description adjusts a modulation level to enable prevention of partial concentration of carriers in a recovery operation. A semiconductor device includes: a semiconductor layer of a first conductivity type; a first impurity layer of the first conductivity type, the first impurity layer being partially diffused in an underside of the semiconductor layer and higher in impurity concentration than the semiconductor layer; and a plurality of second impurity layers of a second conductivity type, the second impurity layers being partially diffused in a surface of the semiconductor layer, wherein the first impurity layer is formed, in a plan view, between the second impurity layers and in a position that does not overlap the second impurity layers, and only the semiconductor layer exists between the second impurity layers in the surface of the semiconductor layer.

An electrical device comprising a substrate of diamond material and elongate metal protrusions extending into respective recesses in the substrate. Doped semiconductor layers, arranged between respective protrusions and the substrate, behave as n type semiconducting material on application of an electric field, between the protrusions and the substrate, suitable to cause a regions of positive space charge within the semiconductor layers.

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*10.sup.15 cm.sup.3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*10.sup.22 cm.sup.4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.

A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.

A transient voltage suppression (TVS) device and method of formation. A TVS device may include a first layer, disposed on a first surface of a substrate, comprising a first P+ layer; a second layer, disposed on a second surface of the substrate, opposite the first surface, comprising a second P+ layer; a third layer, disposed between the first P+ layer and the second P+ layer, comprising an N? layer; and an isolation diffusion region, comprising a P structure, connected to the second P+ layer, and extending along a perimeter of the N? layer.

First and second output transistors are connected in series between a power supply terminal and a ground terminal through an output node connected to an output terminal. An output transistor control circuit is arranged corresponding to at least one of the first and second output transistors and is configured to input a voltage at the output terminal to the gate of the first output transistor at a time of occurrence of disconnection of the power supply terminal and input the same to the gate of the second output transistor at a time of occurrence of disconnection of the ground terminal. The first output transistor has a conductivity type to turn off when a power supply voltage is input to the gate, and the second output transistor has a conductivity type to turn off when a ground voltage is input to the gate.

Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.