A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.

There are disclosed herein various implementations of a photodiode including a silicon substrate, and an N type germanium region situated over the silicon substrate, the N type germanium region being a cathode of the photodiode. In addition, the photodiode includes a P type germanium region situated over the N type germanium region, the P type germanium region being an anode of the photodiode. The photodiode also includes a P type silicon cap over the P type germanium region, an anode contact of the photodiode situated on the P type silicon cap, and one or more cathode contacts of the photodiode electrically connected to the N type germanium region.

A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.

A first region is formed by injecting a first condition type first dopant into a surface layer portion of an IGBT section of a semiconductor substrate. A second region is formed by injecting a second condition type second dopant into a region of the IGBT section shallower than the first region. An amorphous third region is formed by injecting the first conduction type third dopant into a surface layer portion of a diode section at a concentration higher than that of the second dopant. Thereafter, the IGBT section and the diode section are laser-annealed under conditions in which the third region is partially melted and the first dopant is activated. Subsequently, a surface layer portion which is shallower than the second injection region in the entire region of the IGBT section and the diode section is melted and crystallized by annealing the IGBT section and the diode section.

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

A semiconductor body having a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body is provided. At least two trenches extend from the first surface of the semiconductor body through the source region layer and the body region layer. In each of the trenches a gate electrode and a gate dielectric are formed. Diode regions are directly adjacent to each of the at least two trenches. The diode regions extend from the first surface of the semiconductor body through the source region layer and the body region layer. The diode regions include a first region and a second region. A doping concentration in the diode regions varies such that a doping concentration is higher near the first surface than at the bottom of the trench.

A preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna includes: (a) selecting an SOI substrate; (b) etching the SOI substrate to form a platform-shaped active region; (c) depositing a P-type Si material and an N-type Si material around the platform-shaped active region by an in-situ doping process to form a P region and an N region respectively; (d) depositing a polysilicon material around the platform-shaped active region; (e) forming leads on a surface of the polysilicon material and forming PADs by photolithography, to form the P-I-N diode string. Therefore, a high-performance platform-shaped active region based P-I-N diode string suitable for a solid-state plasma antenna can be provided by an in-situ doping process.

A manufacturing method of a diode includes depositing an epitaxial layer and an oxidation structure on a substrate; etching the epitaxial layer to form active trenches and a termination trench using a configuration of the oxidation structure, wherein the termination trench has a first sidewall, a second sidewall, and a bottom portion; performing a thermal oxidation procedure to deposit a trench oxide layer to cover a sidewall and a bottom portion of each active trench, the first sidewall, the second sidewall, and the bottom portion; depositing a semiconductor layer on each active trench, the first sidewall, and the second sidewall to fill the semiconductor layer in each active trench and cover the first sidewall and the second sidewall; and depositing a metal silicide layer on each active trench, and covering the semiconductor layer of the first sidewall and the second sidewall by the metal silicide layer.

Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n.sup. drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n.sup. drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.