A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.

A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

A semiconductor device structure is provided. The semiconductor device structure includes a collector element formed in or over a semiconductor substrate. The semiconductor device structure also includes a semiconductor element over the collector element, and the semiconductor element has a top surface, a bottom surface, and a side surface. The semiconductor device structure further includes an emitter element over the top surface of the semiconductor element. In addition, the semiconductor device structure includes a base element over the collector element and in direct contact with the side surface of the semiconductor element.

A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.

A method for modeling excess base current in irradiated bipolar junction transistors (BJTs) is provided. The method includes quantifying defect-related electrostatic effects of a BJT device to help improve accuracy in predicting an irradiated excess base current of the BJT device. In examples discussed herein, the method can be adapted to model the excess base current of a lateral P-type-N-type-P-type (LPNP) BJT device in depleted and/or accumulated surface potential states. The predicted excess base current may be used to qualify or disqualify the BJT device or an electrical circuit including the BJT device for use in a space system(s) as a commercial-off-the-shelf (COTS) component. By modeling the excess base current based on quantifying and utilizing the defect-related electrostatic effects, it may be possible to accurately predict a total-ionizing-dose (TID) response of the BJT device, thus enabling faster and lower-cost qualification of a COTS component(s) for use in the space system(s).