A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.

A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.

Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a source, a gate and a drain located on one side of a substrate, the gate being located between the source and the drain, the gate includes a first end portion and an intermediate portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion being located in the passive region, the first end portion includes a first sub end portion and a second sub end portion. In a first direction, an extension width of the first sub end portion is greater than that of the intermediate portion, and an extension width of the second sub end portion is greater than that of the first sub end portion.

Provided are a transistor with low contact resistivity and a manufacturing method therefor. The transistor includes a substrate, a buffer layer, a channel layer and a barrier layer sequentially stacked, an ion implantation region is formed in a source region and a drain region of the barrier layer, and grooves arranged at intervals are formed in the ion implantation region. Ohmic metal is deposited on a surface of the ion implantation region and in each groove, and the ohmic metal is in contact with a bottom and a side wall of each groove. In this solution, the ohmic metal can be not only in contact with the surface of the ion implantation region, but also in contact with the side wall of each of the grooves, thereby increasing a contact area between the ohmic metal and the semiconductor, and thus reducing the ohmic contact resistivity.

A semiconductor device includes a substrate, a plurality of epitaxial structures and a plurality of gate structures. The substrate includes a plurality of recesses and a plurality of convex portions. Each of the convex portions is located between the two adjacent recesses, in which each of a sidewall of the recesses includes at least two concave portions. Each of the concave portions includes a first inclined plane and an adjacent second inclined plane. The second inclined plane of one of the concave portions is adjacent to a first inclined plane of another one of the concave portions, such that the sidewall has a zig-zag shape. The epitaxial structures are located in the recesses of the substrate respectively. The gate structures are located on the convex portions of the substrate respectively.

A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.

A semiconductor device includes a channel layer and a barrier layer that are sequentially stacked, a doped layer, and a gate structure. The channel layer and the barrier layer each are made of a group III nitride material. The barrier layer includes a gate region. The doped layer is located on a side of the barrier layer that is away from the channel layer. The doped layer is located in the gate region. A material of the doped layer is a group III-V compound including a receptor-type doped element.