According to one embodiment, a nitride semiconductor includes a base body, and a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the base body and the second nitride region. The first nitride region includes a first portion and a second portion. The second portion is between the first portion and the second nitride region. An oxygen concentration in the first portion is higher than an oxygen concentration in the second portion. The oxygen concentration in the second portion is not more than 1×10.sup.18/cm.sup.3. A first thickness of the first portion in a first direction from the first to second nitride regions is thinner than a second thickness of the second portion in the first direction.

According to one embodiment, a semiconductor device includes a substrate, and a first semiconductor layer including magnesium and Al.sub.x1Ga.sub.1-x1N. The first semiconductor layer includes first, second, and third regions. The first region is between the substrate and the third region. The second region is between the first and third regions. A first concentration of magnesium in the first region is greater than a third concentration of magnesium in the third region. A second concentration of magnesium in the second region decreases along a first orientation. The first orientation is from the substrate toward the first semiconductor layer. A second change rate of a logarithm of the second concentration with respect to a change of a position along the first orientation is greater than a third change rate of a logarithm of the third concentration with respect to the change of the position along the first orientation.

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.

In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.

A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.