An apparatus comprising an interposer mounted to a conductive holder and a plurality of microwave cavities, wherein each microwave cavity of the plurality of microwave cavities is comprised of a fin section having two sidewalls, wherein each sidewall is comprised of a vane that extends up from the conductive holder through the interposer.

A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

A Doherty power amplifier and a device are disclosed. In a combiner of the Doherty power amplifier, a first input port and a termination port are open coupled by at least two coupled microstrip lines and/or a second input port and an output port are open coupled by at least two coupled microstrip lines. Therefore, a balanced amplitude bandwidth may be obtained and may be much broader than that of the existing solutions, in addition, a controllable size or a potentially small size may be realized. Furthermore, the Doherty power amplifier in this disclosure may provide large 2.sup.nd harmonic suppression to meet product spectrum mask requirements.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

A radar based, fill-level sensor comprising at least one semiconductor element, including at least a semiconductor chip and a chip package, in which the at least one semiconductor chip is arranged, wherein the at least one semiconductor chip has at least one coupling element, which serves as a signal gate for electromagnetic waves, preferably in the millimeter wave region, characterized in that at least one first resonator structure is arranged on a surface portion of the chip package.

A microcircuit integrating a waveguide with a rectangular cross-section, the microcircuit including a first chip and a second chip assembled on each other, the waveguide being located in a junction zone between chips and extending in parallel to the chips, the waveguide including a first conductive plate located on the side of the first chip and parallel to the first chip, and a second conductive plate, located on the side of the second chip and parallel to the second chip, the waveguide being laterally delimited on one and the other side of the waveguide by one or more electrical connecting elements electrically connecting the first chip to the second chip.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

An electronic device includes a carrier having at least one bonding pad, a plurality of electronic elements disposed on the carrier and one of the electronic elements including a substrate and at least one connecting terminal disposed between the substrate and the carrier. The electronic elements are electrically connected to the at least one bonding pad via the at least one connecting terminal.

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

The present description concerns an electromagnetic wave transmit/receive device comprising a multilayer organic substrate, an integrated circuit chip, flip-chip assembled on the multilayer organic substrate, a package comprising a first cavity, containing the multilayer organic substrate and the integrated circuit chip, and communicating over a channel with a second cavity forming a waveguide for electromagnetic waves.