A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.

A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor device is disposed on the substrate. The semiconductor device includes a first lateral surface. The underfill is disposed between the substrate and the semiconductor device. The underfill includes a first lateral surface. The first lateral surface of the underfill and the first lateral surface of the semiconductor device are substantially coplanar.

A manufacturing method of an array substrate includes forming a plurality of bonding pads in a bonding region of a base substrate, and forming at least one insulating support part at at least one position where the plurality of bonding pads are not provided in the bonding region of the base substrate.

Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

An electronic device includes a substrate, an electronic component provided in a first area of the substrate, a spacer provided between the substrate and the electronic component so as to come into contact with the substrate and the electronic component, a first bonding element provided between the substrate and the electronic component so as to bond the substrate and the electronic component, a second bonding element provided between the substrate and the electronic component so as to bond the substrate and the electronic component, the second bonding element having a height higher than a height of the first bonding element, and a stress generation source provided outside the first area of the substrate to generate a stress in the first area of the substrate, the stress generation source being located closer to the second bonding element than to the first bonding element.

An assembly platform for arrangement as an interposer device between an integrated circuit and a substrate to interconnect the integrated circuit and the substrate through the assembly platform, the assembly platform comprising: an assembly substrate; a plurality of conducting vias extending through the assembly substrate; at least one nanostructure connection bump on a first side of the assembly substrate, the nanostructure connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate, wherein each of the nanostructure connection bumps comprises: a plurality of elongated conductive nanostructures vertically grown on the first side of the assembly substrate, wherein the plurality of elongated nanostructures are embedded in a metal for the connection with at least one of the integrated circuit and the substrate, at least one connection bump on a second side of the assembly substrate, the second side being opposite to the first side, the connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate.

Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad.