H01L2224/26135

SEMICONDUCTOR PACKAGE
20210082881 · 2021-03-18 ·

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Package structure and method and equipment for forming the same

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

Chip package structure and method for forming the same

A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.

Die Stack Arrangement Comprising a Die-Attach-Film Tape and Method for Producing Same
20210005568 · 2021-01-07 ·

A device includes a base substrate with a sensor component arranged thereon; a spacer layer on the base substrate, wherein the spacer layer is structured in order to predefine a cavity region, in which the sensor component is arranged in an exposed fashion on the base substrate, and a DAF tape element (DAF=Die-Attach-Film) on a stack element, wherein the DAF tape element mechanically fixedly connects the stack element to the spacer layer arranged on the base substrate and to obtain the cavity region.

Die stack arrangement comprising a die-attach-film tape and method for producing same

A device includes a base substrate with a sensor component arranged thereon; a spacer layer on the base substrate, wherein the spacer layer is structured in order to predefine a cavity region, in which the sensor component is arranged in an exposed fashion on the base substrate, and a DAF tape element (DAF=Die-Attach-Film) on a stack element, wherein the DAF tape element mechanically fixedly connects the stack element to the spacer layer arranged on the base substrate and to obtain the cavity region.

Semiconductor package structure

A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Imaging module can easily and stably connect an imaging-sensing device to a coaxial cable
10804620 · 2020-10-13 · ·

An imaging module of the invention includes: an image-sensing device that has a light-receiving face, a terminal surface located on an opposite side of the light-receiving face, and a plurality of image-sensing terminals provided on the terminal surface; a support that has a first end disposed on the terminal surface, a second end disposed on an opposite side of the first end, a side face disposed between the first end and the second end, and a guide disposed on the side face so as to correspond to positions of the image-sensing terminals and that is formed of an insulator; a coaxial cable including a conductor disposed on the guide; and solder that electrically connects the conductor to an image-sensing terminal corresponding to the conductor on the guide.

SEMICONDUCTOR PACKAGES INCLUDING DIE OVER-SHIFT INDICATING PATTERNS
20200286838 · 2020-09-10 · ·

A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.

SEMICONDUCTOR PACKAGE WITH DIE STACKED ON SURFACE MOUNTED DEVICES
20200219799 · 2020-07-09 ·

One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.