A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A semiconductor package includes a first semiconductor chip on a base chip, a second semiconductor chip on the first semiconductor chip in a first direction, each of the first and second semiconductor chips including a TSV and being electrically connected to each other via the TSV, dam structures on the base chip and surrounding a periphery of the first semiconductor chip, a first adhesive film between the base chip and the first semiconductor chip, a portion of the first adhesive film filling a space between the first semiconductor chip and the dam structures, a second adhesive film between the first semiconductor chip and the second semiconductor chip, a portion of the second adhesive film overlapping the dam structures in the first direction, and an encapsulant encapsulating a portion of each of the dam structures, the first semiconductor chip, and the second semiconductor chip.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.

An image sensor package includes: a package base substrate having a cavity extending inwards from an upper surface thereof, and including a plurality of upper surface connection pads and a plurality of lower surface connection pads; an image sensor chip in the cavity, and including a chip body having a first surface and a second surface facing each other, a sensor unit located in the first surface of the chip body, and a plurality of chip pads around the sensor unit; a filter glass above the image sensor chip, and including a transparent substrate and a plurality of redistribution patterns on a lower surface of the transparent substrate; and a plurality of connection terminals between the plurality of redistribution patterns and the plurality of chip pads and between the plurality of redistribution patterns and the plurality of upper surface connection pads.

A semiconductor package includes spread inhibiting structure to constrain the movement of viscous material during fabrication. In some embodiments, the spread inhibiting structure comprises a recess in an underside of a package lid overlying the die. According to other embodiments, the spread inhibiting structure comprises polymer disposed on the lid underside proximate to a side of the packaged die. According to still other embodiments, the spread inhibiting structure comprises a polymer disposed around the top of the die to serve as a dam and contain spreading. In some embodiments, the viscous material may be a Thermal Integration Material (TIM) in an uncured state, and the polymer may be the TIM in a cured state.

A semiconductor device includes: a plurality of semiconductor chips stacked on a substrate in a vertical direction; a filler structure including a plurality of horizontal underfill layers formed between adjacent semiconductor chips of the plurality of semiconductor chips and between the substrate and the stack of semiconductor chips, and including underfill sidewalls formed around the horizontal underfill layers and the plurality of semiconductor chips; and a molding resin surrounding the plurality of semiconductor chips at least on side surfaces of the plurality of semiconductor chips. The underfill sidewalls include a recess pattern, which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips, and is recessed in a direction parallel to an upper surface of the substrate at locations where the recess pattern meets the substrate.

In order to achieve the above-described objects, according to an aspect of the present disclosure, a display device includes a substrate which includes an active area and a non-active area extending from the active area and including a pad area and is formed of any one of a transparent conducting oxide and an oxide semiconductor; a plurality of inorganic insulating layers disposed on the substrate; a dam member having one end disposed on the pad area and the other end disposed at the outside of the substrate; and a plurality of flexible films which is disposed to cover the dam member and has one end disposed in the pad area. Accordingly, the dam member which covers the pad area is formed to minimize the crack of the plurality of inorganic insulating layers at the edge of the substrate.

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

A performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip, and a clip mounted on the semiconductor chip via a silver paste. Here, the semiconductor chip includes a passivation film having an opening, a source pad of a main transistor having a portion exposed from the passivation film at the opening, and a wall portion provided on the passivation film so as to surround the source pad in a plan view. At this time, a whole of the portion (exposed surface) of the source pad, which is exposed from the passivation film, is covered with the silver paste. Further, in the plan view, the silver paste connecting the source pad with the clip is positioned inside of an area surrounded by the wall portion, without overflowing.