Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

In the joined body (10) in which the conductor (12) and the substrate (14) are joined by the joining material (13), the joining material (13) includes a sintered body formed by sintering silver powder. A sintered body having a porosity of 8% to 30% and a surface roughness Ra of a joining surface of 500 nm or more and 3.3 μm or less is adopted.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

A collet for compressing an adhesive-attached chip, the collet including a main body having a first pressing surface to which a pressing force from a compressing device is directly transmitted, and a projecting portion projecting from the main body and having a second pressing surface provided along an outer circumference of the first pressing surface, the first pressing surface and the second pressing surface forming a holding surface for holding the adhesive-attached chip.

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties.

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.

The present disclosure relates to an adhesive transfer film for bonding a semiconductor chip and a spacer to a substrate and a method for manufacturing a power module substrate by using same, the adhesive transfer film being obtained by manufacturing an Ag sintering paste in the form of a film. The present disclosure can reduce the process time by minimizing a sintering process, and can reduce equipment investment cost.