An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

A sintering paste includes solvent and nanomicrocrystallite (NMC) particles. Each NMC particle is a single crystallite having at least one dimension in the range of 1 nm to 100 nm and at least one dimension in the range of 0.1 μm to 1000 μm. The sintering paste may be used in a pressureless sintering process to form a low porosity joint having high bond strength, high electrical and thermal conductivity, and high thermal stability.

A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark off each of chip placement regions on the front surface side of the wafer, a liquid supplying step of supplying a liquid to the chip placement regions, a chip placing step of placing the chips on the liquid to position the chips in the chip placement regions by the surface tension of the liquid after carrying out the liquid supplying step, and a liquid removing step of removing the liquid to arrange the plurality of chips on the wafer after carrying out the chip placing step.

Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device according to an embodiment of the inventive concept includes a first semiconductor chip having a recess portion in one surface thereof; a first adhesion pattern filled within the recess portion of the first semiconductor chip; and a second semiconductor chip disposed on the first adhesion pattern. The second semiconductor chip may represent improved heat dissipation characteristics.

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film 1 which comprises a substrate 3 and an adhesive layer 5, wherein the storage elastic modulus at 180° C. of the substrate 3 is from 10 to 100 MPa, and the adhesive layer 5 is a reaction cured product of a composition for adhesive layer comprising a specific acrylic polymer and a polyfunctional isocyanate compound, wherein the number of moles M.sub.OH of hydroxy groups and the number of moles M.sub.COOH of carboxy groups, derived from the acrylic polymer, and the number of moles M.sub.NCO of isocyanate groups derived from the polyfunctional isocyanate compound, satisfy a specific relation, and which is suitable as a mold release film for producing a semiconductor element.

The present technology relates to a solid-state imaging device, an imaging apparatus, an electronic apparatus, and a semiconductor device, which can prevent overflow of an underfilling resin filled in a portion adapted to connect the substrate to the flip chip and can prevent secondary damages such as electric short-circuit and contact with processing equipment. By utilizing a molding technology of forming an on-chip lens, a dam is formed in a ring shape or a square shape in a manner surrounding a range where a flip chip is connected via a solder bump on an upper layer of a substrate of the solid-state imaging device and provided in order to form the on-chip lens. This can block the underfilling resin filled in the range where the substrate and the flip chip are electrically connected. The present technology can be applied to a solid-state imaging device.