A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.1 to 4,000 cm.sup.1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.1 to 550 cm.sup.1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.1 to 4,000 cm.sup.1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.1 to 550 cm.sup.1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

The invention relates to a method in which a layer compound having a substrate having an adhesive layer applied thereon at least in regions is provided. An opening extending through the substrate and through the adhesive layer is introduced therein in order to obtain a patterned layer compound. A microchip having an active region arranged on the outside of the chip is provided, wherein the active region is a sensor area or a radiation coupling-out area. In addition, in accordance with the invention, the microchip is arranged on the adhesive layer of the patterned layer compound such that the active region is exposed through the opening.

Provided is an inkjet adhesive which is applied using an inkjet device, wherein the adhesive can suppress generation of voids in the adhesive layer and, after bonding, can reduce an outgas at the time of being exposed to high temperatures, and can enhance moisture-resistant reliability. An inkjet adhesive according to the present invention comprises a first photocurable compound having one (meth)acrylol group, a second photocurable compound having two or more (meth)acrylol groups, a photo-radical initiator, a thermosetting compound having one or more cyclic ether groups or cyclic thioether groups, and a compound capable of reacting with the thermosetting compound, and the first photocurable compound contains alkyl (meth)acrylate having 8 to 21 carbon atoms.

A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein. The local interconnect component includes TSVs penetrating through a substrate and electrically coupled to first and second conductive connectors, the first conductive connectors between the first redistribution structure and a first side of the substrate, the second conductive connectors between the second redistribution structure and a second side of the substrate, and a first insulating layer between the first redistribution structure and the first side and laterally covering the first conductive connectors.

A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein. The local interconnect component includes TSVs penetrating through a substrate and electrically coupled to first and second conductive connectors, the first conductive connectors between the first redistribution structure and a first side of the substrate, the second conductive connectors between the second redistribution structure and a second side of the substrate, and a first insulating layer between the first redistribution structure and the first side and laterally covering the first conductive connectors.

A method for forming a chip package structure is provided. The method includes providing an electrical substrate and a photonic substrate over and bonded to the electrical substrate. The method includes partially removing the dielectric structure to form a first through hole and a second through hole in the dielectric structure. The first through hole passes through the dielectric structure and exposes the first wiring layer. The method includes forming a first conductive via structure and a second conductive via structure in the first through hole and the second through hole respectively. The first conductive via structure is in direct contact with the first wiring layer, and the second conductive via structure is spaced apart from the first wiring layer.