An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

An electronic device includes a substrate and a wiring. The wiring is provided above the substrate and includes a NiB layer and a copper layer provided on the NiB layer. The NiB layer contains 3.2% by weight to 5% by weight of boron.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

An optical module includes a semiconductor chip, a first gold-tin layer formed over the semiconductor chip and having gold and tin as main components, a barrier layer formed over the first gold-tin layer, having slower diffusion velocity into tin than diffusion velocity of gold into tin, and having electric conductivity, a second gold-tin layer formed over the barrier layer and having gold and tin as main components, and an optical device provided over the second gold-tin layer.

An optical module includes a semiconductor chip, a first gold-tin layer formed over the semiconductor chip and having gold and tin as main components, a barrier layer formed over the first gold-tin layer, having slower diffusion velocity into tin than diffusion velocity of gold into tin, and having electric conductivity, a second gold-tin layer formed over the barrier layer and having gold and tin as main components, and an optical device provided over the second gold-tin layer.

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.