A chip on film package includes a chip and a flexible substrate having a film and a circuit layer. The circuit layer is formed on a first surface of the film and electrically connected to the chip. At least one groove is recessed on a second surface of the film. The flexible substrate is bent to form flat portions and at least one curved portion located between the flat portions when it is bonded to external electronic components. The groove is located on the curved portion and provided to protect the curved portion of the flexible substrate from breaking.

A chip on film package includes a chip and a flexible substrate having a film and a circuit layer. The circuit layer is formed on a first surface of the film and electrically connected to the chip. At least one groove is recessed on a second surface of the film. The flexible substrate is bent to form flat portions and at least one curved portion located between the flat portions when it is bonded to external electronic components. The groove is located on the curved portion and provided to protect the curved portion of the flexible substrate from breaking.

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

A method for manufacturing an electronic assembly features a semiconductor device with a first side and a second side opposite the first side to facilitate enhanced thermal dissipation. The first side has a first conductive pad. The second side has a primary metallic surface. By heating the assembly once, a first substrate (e.g. lead frame) is bonded to a first conductive pad via first metallic bonding layer; and second substrate (e.g., heat sinking circuit board) is bonded to a primary metallic surface via a second metallic bonding layer. In one configuration the second metallic bonding layer is composed of solder and copper, for example.

A method for manufacturing an electronic assembly features a semiconductor device with a first side and a second side opposite the first side to facilitate enhanced thermal dissipation. The first side has a first conductive pad. The second side has a primary metallic surface. By heating the assembly once, a first substrate (e.g. lead frame) is bonded to a first conductive pad via first metallic bonding layer; and second substrate (e.g., heat sinking circuit board) is bonded to a primary metallic surface via a second metallic bonding layer. In one configuration the second metallic bonding layer is composed of solder and copper, for example.

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

A method of applying a die attach material includes forming a wafer stencil by selectively removing on the back side of a wafer including a plurality of semiconductor die having an active top side a predetermined depth to form a recess having an inner circumference while not removing an outer most circumference of the wafer. The recess is filled with a B-stage adhesive material. The wafer is singulated to form a plurality singulated semiconductor die. The singulated semiconductor die is die attached back side down to a package substrate, and then the B-stage adhesive material is cured. The B-stage adhesive material across its full area generally has a minimum thickness of at least 20 m and a maximum thickness range of 6 m.

A method of applying a die attach material includes forming a wafer stencil by selectively removing on the back side of a wafer including a plurality of semiconductor die having an active top side a predetermined depth to form a recess having an inner circumference while not removing an outer most circumference of the wafer. The recess is filled with a B-stage adhesive material. The wafer is singulated to form a plurality singulated semiconductor die. The singulated semiconductor die is die attached back side down to a package substrate, and then the B-stage adhesive material is cured. The B-stage adhesive material across its full area generally has a minimum thickness of at least 20 m and a maximum thickness range of 6 m.