A semiconductor device includes: a semiconductor base body; a semiconductor chip; a sintering material layer bonded to a lower surface of the semiconductor chip and having a thickness decreasing toward an outer periphery of the semiconductor chip; and a conductive plate having a main surface facing the lower surface of the semiconductor chip and a recessed portion which the sintering material layer contacts in the main surface, the recessed portion having a depth decreasing toward the outer periphery of the semiconductor chip.

The present invention provides a conductive bonded assembly utilizing particles of Ni or an Ni alloy as conductive particles so as to enable firing under non-pressing conditions and further realize an excellent bonding strength, electron migration characteristic, and ion migration characteristic. The conductive bonded assembly of the present invention is a conductive bonded assembly of an electronic component which has a first bondable member (for example, electrode material), a second bondable member (for example, a semiconductor device on an Si or SiC substrate), and a conductive bonding layer bonding these bondable members together, where the bonding layer is an Ni sintered body formed by a sintered body of Ni particles which has a porosity of 30% or less, and, further, can be obtained by heating and sintering the Ni particles at the time of firing where the Ni sintered bonding layer is formed.

A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.

PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.

A die and substrate assembly is disclosed for a die with electronic circuitry and a substrate. A sintered bonding layer of sintered metal is disposed between the die and the substrate. The sintered bonding layer includes a plurality of zones having different sintered metal densities. The plurality of zones are distributed along one or more horizontal axes of the sintered bonding layer, along one or more vertical axes of the sintered bonding layer or along both one or more horizontal and one or more vertical axes of the sintered bonding layer.