An electronic device includes a substrate, a bump, a chip, and an adhesive layer. The substrate includes a first connection pad. The bump is disposed on the first connection pad. The chip includes a second connection pad. The bump is disposed between the first connection pad and the second connection pad. The adhesive layer is disposed between the substrate and the chip. A dissipation factor of the adhesive layer is less than or equal to 0.01 at a frequency of 10 GHz. A manufacturing method of an electronic device includes the following: providing a substrate, where the substrate includes a first connection pad; applying an adhesive layer on the substrate; patterning the adhesive layer, such that the adhesive layer produces an opening exposing the first connection pad; forming a bump on the first connection pad; and bonding the chip onto the bump through the second connection pad.

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.

A semiconductor device includes: a plurality of semiconductor chips stacked on a substrate in a vertical direction; a filler structure including a plurality of horizontal underfill layers formed between adjacent semiconductor chips of the plurality of semiconductor chips and between the substrate and the stack of semiconductor chips, and including underfill sidewalls formed around the horizontal underfill layers and the plurality of semiconductor chips; and a molding resin surrounding the plurality of semiconductor chips at least on side surfaces of the plurality of semiconductor chips. The underfill sidewalls include a recess pattern, which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips, and is recessed in a direction parallel to an upper surface of the substrate at locations where the recess pattern meets the substrate.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, an under-fill fillet on side surfaces of the plurality of semiconductor devices, and a molding resin surrounding the plurality of semiconductor devices. An uppermost end of the under-fill fillet includes a planar surface coplanar with an upper surface of a periphery of an uppermost semiconductor device among the plurality of semiconductor devices, and the molding resin completely covers the planar surface.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A die bonding structure is provided. The die bonding structure includes a chip, an adhesive layer under the chip, a bonding layer under the adhesive layer, and a heat dissipation substrate under the bonding layer. The bonding layer includes a silver nano-twinned thin film, which has parallel-arranged twin boundaries. The parallel-arranged twin boundaries include at least 90% of [111] crystal orientation.

A die bonding structure is provided. The die bonding structure includes a chip, an adhesive layer under the chip, a bonding layer under the adhesive layer, and a heat dissipation substrate under the bonding layer. The bonding layer includes a silver nano-twinned thin film, which has parallel-arranged twin boundaries. The parallel-arranged twin boundaries include at least 90% of [111] crystal orientation.

The semiconductor device according to the present disclosure has features (1) to (3) below. The feature (1) is that “a lower surface of an on-chip bonding material has a shape matching a surface shape of a main current wiring connection region in plan view”. The feature (2) is that “an emitter sense wiring is directly connected to a side surface of the main current wiring connection region”. The feature (3) is that “an IGBT chip has an ineffective region in which the IGBT does not function in a region below an emitter sense pad and the emitter sense wiring”.

A semiconductor device includes an insulated circuit board having a conductive pattern layer, a sintered member disposed on the conductive pattern layer, a semiconductor chip placed on the sintered member, and a coating material covering the semiconductor chip. The sintered member has, on a surface thereof opposite to the conductive pattern layer, a frame shaping the outer edge of a recess. The semiconductor chip is mounted in the recess such that its top face is located closer to the conductive pattern layer than a top end of the frame.