An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

According to one embodiment, a semiconductor device includes: a circuit board; a first semiconductor chip mounted on a face of the circuit board; a resin film covering the first semiconductor chip; and a second semiconductor chip having a chip area larger than a chip area of the first semiconductor chip, the second semiconductor chip being stuck to an upper face of the resin film and mounted on the circuit board. The resin film entirely fits within an inner region of a bottom face of the second semiconductor chip when viewed in a stacking direction of the first and second semiconductor chips.

A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.

A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.

A bonding film for bonding a semiconductor element and a substrate. The bonding film has an electroconductive bonding layer formed by molding an electroconductive paste including metal fine particles (P) into a film form, and a tack layer having tackiness and laminated on the electroconductive bonding layer. The tack layer includes 0.1% to 1.0% by mass of metal fine particles (M) with respect to the metal fine particles (P) in the electroconductive bonding layer, and the metal fine particles (M) have a melting point of 250° C. or lower.

A bonding film for bonding a semiconductor element and a substrate. The bonding film has an electroconductive bonding layer formed by molding an electroconductive paste including metal fine particles (P) into a film form, and a tack layer having tackiness and laminated on the electroconductive bonding layer. The tack layer includes 0.1% to 1.0% by mass of metal fine particles (M) with respect to the metal fine particles (P) in the electroconductive bonding layer, and the metal fine particles (M) have a melting point of 250° C. or lower.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

A printed circuit board includes: a first insulating layer; a first cavity disposed in one surface of the first insulating layer; a plurality of protrusion portions spaced apart from each other in the first cavity; and a first wiring layer embedded in the one surface of the first insulating layer.