A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.