Patent classifications
H01L2224/484
Systems and methods for optimizing looping parameters and looping trajectories in the formation of wire loops
A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).
Method of manufacturing a semiconductor device
A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
Method of manufacturing a semiconductor device
A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
Production of a multi-chip component
A method of producing a surface-mountable multi-chip component includes providing a chip arrangement including a metallic conductor structure exposed at a rear side, a plurality of semiconductor chips and an housing material; and forming a solder stop coating on a rear side of the chip arrangement, wherein the solder stop coating separates connection regions of the conductor structure.
Semiconductor devices and methods for forming a semiconductor device
A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.
Lead and lead frame for power package
A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.
Lead and lead frame for power package
A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.
Light-emitting arrangement and light-emitting system
Described is an arrangement and system for precise angular and directional positioning of light-emitting diodes (LED). An LED component includes a base body with a light-emitting region, a first connector, and a second connector, where the connectors are electrically conductively connected to the light-emitting region. The base body includes at least two fixing regions and the connectors each include a bending portion and a contact area for surface mounting. Each of the bending portions is arranged between the base body and the contact area. A supporting frame includes a plinth region to align the supporting frame on a surface and includes an outwardly open recess, a support region to receive a component in the supporting frame and at least two fixing elements to fix the component above the support region. A base area of the plinth region and a base area of the support region enclose an acute angle.
Light-emitting arrangement and light-emitting system
Described is an arrangement and system for precise angular and directional positioning of light-emitting diodes (LED). An LED component includes a base body with a light-emitting region, a first connector, and a second connector, where the connectors are electrically conductively connected to the light-emitting region. The base body includes at least two fixing regions and the connectors each include a bending portion and a contact area for surface mounting. Each of the bending portions is arranged between the base body and the contact area. A supporting frame includes a plinth region to align the supporting frame on a surface and includes an outwardly open recess, a support region to receive a component in the supporting frame and at least two fixing elements to fix the component above the support region. A base area of the plinth region and a base area of the support region enclose an acute angle.
SEMICONDUCTOR DEVICE, POWER CONVERTER, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING POWER CONVERTER
There is provided a semiconductor device including an insulating substrate provided with a circuit surface, and an external terminal bonded to the circuit surface. The circuit surface has an upper surface that is in contact with and bonded to a part of a lower surface of the external terminal. In at least a part of a portion where the upper surface of the circuit surface and the lower surface of the external terminal are in contact with each other, a melted portion of the circuit surface and the external terminal is formed. A gap between the upper surface of the circuit surface and the lower surface of the external terminal has a size of 20 m or less. The circuit surface and the external terminal are each made of copper or copper alloy.