A display device including a substrate including a wiring electrode; a conductive adhesive layer including an anisotropic conductive medium, and disposed to cover the wiring electrode; and a plurality of semiconductor light emitting devices adhered to the conductive adhesive layer and electrically connected to the wiring electrode through the anisotropic conductive medium. Further, the conductive adhesive layer includes a first layer disposed on the substrate; a second layer deposited on the first layer and including the anisotropic conductive medium; and a third layer deposited on the second layer, to which the semiconductor light emitting devices are adhered. Further, at least one of the second layer and the third layer includes a white pigment configured to reflect light emitted by the semiconductor light emitting device.

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

A method for manufacturing a micro LED display is provided. The method includes providing a plurality of LED elements on a first substrate, transferring, using a magnetic holder or a vacuum holder, at least two of the plurality of LED elements of the same primary color from the first substrate to a second substrate, performing the steps of the providing and the transferring with respect to three primary colors, forming an array of RGB LED units on the second substrate, each of the array of RGB LED units including a red LED element, a green LED element, and a blue LED element, interposing the array of RGB LED units between the second substrate and an LED driver wafer, detaching the second substrate from the array of RGB LED units, and interposing the array of RGB LED units between the LED driver wafer and a cover.

A method for manufacturing a micro LED display is provided. The method includes providing a plurality of LED elements on a first substrate, transferring, using a magnetic holder or a vacuum holder, at least two of the plurality of LED elements of the same primary color from the first substrate to a second substrate, performing the steps of the providing and the transferring with respect to three primary colors, forming an array of RGB LED units on the second substrate, each of the array of RGB LED units including a red LED element, a green LED element, and a blue LED element, interposing the array of RGB LED units between the second substrate and an LED driver wafer, detaching the second substrate from the array of RGB LED units, and interposing the array of RGB LED units between the LED driver wafer and a cover.

A display device including a substrate including a wiring electrode; a conductive adhesive layer including an anisotropic conductive medium, and disposed to cover the wiring electrode; and a plurality of semiconductor light emitting devices adhered to the conductive adhesive layer and electrically connected to the wiring electrode through the anisotropic conductive medium. Further, the conductive adhesive layer includes a first layer disposed on the substrate; a second layer deposited on the first layer and including the anisotropic conductive medium; and a third layer deposited on the second layer, to which the semiconductor light emitting devices are adhered. Further, at least one of the second layer and the third layer includes a white pigment configured to reflect light emitted by the semiconductor light emitting device.

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.