A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250 C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

A process for obtaining a bonding surface for direct bonding includes: a) providing a substrate based on a sintered metal having a base surface with an RMS roughness lower than 6 nanometers and a PV roughness lower than 100 nanometers; b) bombarding the base surface with ionic species; c) depositing a metal layer on the base surface; and d) carrying out a mechanical and/or chemical polish of an exposed surface of the metal layer. A structure including a substrate based on a sintered metal the base surface of which is at least partially formed from a metal including ionic species implanted by bombardment of the base surface, and a metal layer of identical chemical composition to that of the metal base substrate and including a bonding surface with an RMS roughness lower than 0.6 nanometers and a PV roughness lower than 10 nanometers is also provided.

A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.

A bonding system includes a substrate transfer device configured to transfer a first substrate and a second substrate to a bonding apparatus, a first holding plate configured to hold the first substrate from an upper surface side, and a second holding plate disposed below the first holding plate and configured to hold the second substrate from a lower surface side so that the second substrate faces the first substrate. The substrate transfer device includes a first holding part capable of holding the first substrate from the upper surface side, and a second holding part disposed below the first holding part and capable of holding the second substrate from the lower surface side. The first holding part and the second holding part are configured to receive and hold the first substrate and the second substrate at the same time from the first holding plate and the second holding plate.

A bonding system includes a substrate transfer device configured to transfer a first substrate and a second substrate in a normal pressure atmosphere, a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate to be bonded with each other in a depressurized atmosphere, a load lock chamber in which the first substrate and the second substrate are delivered between the substrate transfer device and the surface modifying apparatus and in which an internal atmosphere of the load lock chamber is switchable between an atmospheric pressure atmosphere and the depressurized atmosphere, a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate, and a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force.

IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. Optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. An opening in the insulator material may be formed to expose a surface of a die attach feature. The exposed surface may be selectively roughened, and an IC die attached to the roughened surface.