A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is Ra, 0.8 mRa3.0 m holds.

A product disclosed herein includes an RF filter die including an RF filter, a front side and a plurality of conductive bond pads conductively coupled to at least a portion of the RF filter, wherein at least a portion of the conductive bond pads is exposed on the front side of the RF filter die. The product also includes a TSV (Through-Substrate-Via) die that includes a plurality of conductive TSV contacts positioned on a back side of the TSV die and at least one conductive TSV (Through-Substrate-Via) structure that is conductively coupled to at least one of the plurality of conductive TSV contacts, wherein the back side of the TSV die is bonded to the front side of the RF filter such that the conductive bond pads on the RF filter die are conductively coupled to corresponding conductive TSV contacts positioned on the back side of the TSV die.

According to one aspect, there is proposed a method for assembling two integrated circuit wafers. The method includes removing by abrasion of a portion of an assembly face of a first wafer on a perimeter of the first wafer, and bonding the assembly face of the first wafer to an assembly face of a second integrated circuit wafer.

A power electronics method and assembly produced by the method. The assembly has a substrate, having a power semiconductor element, and an adhesion layer disposed therebetween, wherein the substrate has a first surface that faces a power semiconductor element, a power semiconductor element has a third surface that faces the substrate, the adhesion layer has a second surface which, preferably across the full area, contacts the third surface and has a first consistent surface contour having a first roughness, and wherein a fourth surface of the power semiconductor element that is opposite the third surface has a second surface contour having a second roughness, said second surface contour following the first surface contour.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250 C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

A process for obtaining a bonding surface for direct bonding includes: a) providing a substrate based on a sintered metal having a base surface with an RMS roughness lower than 6 nanometers and a PV roughness lower than 100 nanometers; b) bombarding the base surface with ionic species; c) depositing a metal layer on the base surface; and d) carrying out a mechanical and/or chemical polish of an exposed surface of the metal layer. A structure including a substrate based on a sintered metal the base surface of which is at least partially formed from a metal including ionic species implanted by bombardment of the base surface, and a metal layer of identical chemical composition to that of the metal base substrate and including a bonding surface with an RMS roughness lower than 0.6 nanometers and a PV roughness lower than 10 nanometers is also provided.

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

A method of fabricating a printed circuit film including the steps of preparing a base film, and a plurality of lead wires disposed on the base film, the plurality of lead wires spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, and forming a bonding member including a conductive member disposed to overlap a central portion of each of the plurality of lead wires, a first non-conductive member disposed to overlap a first portion of the plurality of lead wires in the second direction, and a second non-conductive member disposed to overlap a second portion of the plurality of lead wires in the second direction.