A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.−1 to 4,000 cm.sup.−1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.−1 to 550 cm.sup.−1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

The invention relates to an apparatus for especially thermally joining micro-electromechanical parts (2, 3) in a process chamber (8), comprising a bottom support plate (11) for holding at least one first (2) of the parts (2, 3) to be joined, and a pressing device (15) for applying pressure to at least one second (3) of the parts (2, 3) to be joined in relation to the at least one first part (2). The pressing device (15) is equipped with an expandable membrane (19) provided for entering in contact with the at least one second part (3). Fluid pressure, in particular gas pressure, can be applied to said membrane (19) on the side thereof facing away from the parts (2, 3) to be joined.

A bonding structure bonds a Cu wiring line and a device electrode with each other. The bonding structure is arranged between the Cu wiring line and the device electrode, and comprises a first intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the Cu wiring line, a second intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the device electrode, and an intermediate layer that is present between the intermetallic compound layers. In the intermediate layer, a network-like IMC (a network-like intermetallic compound of Cu and Sn) is present in Sn.

An object is to provide highly reliable semiconductor element bonding portion and semiconductor device that have high heat resistance and improved adhesion between a bonding material and a sealing resin. Provided is a semiconductor element bonding portion in which the semiconductor element 11 and an electrically conductive plate 123a are bonded to each other by a bonding layer 10 and the bonding layer 10 includes a metal nanoparticle sintered body 101 and a coupling agent 102 including an SH group.

A method for the production of a silver sintering agent in the form of a layer-shaped silver sintering body having silver oxide surfaces and the use thereof are provided.

A method for the production of a silver sintering agent in the form of a layer-shaped silver sintering body having silver oxide surfaces and the use thereof are provided.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or silver are bonded to each other. The aluminum member is constituted by an aluminum alloy in which a Si concentration is set to be in a range of 1 mass % to 25 mass %. A Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding.

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.