A mounting device comprises a substrate stage, a mounting head, an elevating unit, a recognition mechanism, and a control unit. The recognition mechanism acquires position information about a chip recognition mark and a substrate recognition mark using an imaging unit. The control unit calculates an amount of positional deviation between a chip component and a substrate from the position information about the chip recognition mark and the substrate recognition mark, and performs alignment by driving the mounting head and/or the substrate stage according to the amount of the positional deviation. The chip component and the substrate are brought closer with each other and the alignment is performed in a state in which the imaging unit simultaneously images the chip recognition mark and the substrate recognition mark within a depth of field, after which the chip component and the substrate are brought into close contact with each other.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.

The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a is bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure. A corresponding method for aligning two or more semiconductor structures for coupling is also provided.

A method for manufacturing a display device includes preparing a display device including a display panel including a first alignment mark and a first circuit board including a second alignment mark and on one end of the display panel, disposing the display device on a stage including a base mark, setting the base mark as a reference mark in consideration of a relative position relation between the first alignment mark and the base mark by sensing the first alignment mark and the base mark, and determining a bending state of the display device by sensing the base mark and the second alignment mark and identifying a position relation between the base mark and the second alignment mark.

A semiconductor manufacturing apparatus includes a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips; a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator; a pickup unit picking up each of the plurality of semiconductor chips; and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit; wherein the pickup unit moves the semiconductor chip from the stage to a mounting position of a supporting substrate and adherers the semiconductor chip by the control unit.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.