Patent classifications
H01L2224/83132
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.
METHOD FOR MANUFACTURING DISPLAY DEVICE AND APPARATUS FOR MANUFACTURING DISPLAY DEVICE
A method for manufacturing a display device includes preparing a display device including a display panel including a first alignment mark and a first circuit board including a second alignment mark and on one end of the display panel, disposing the display device on a stage including a base mark, setting the base mark as a reference mark in consideration of a relative position relation between the first alignment mark and the base mark by sensing the first alignment mark and the base mark, and determining a bending state of the display device by sensing the base mark and the second alignment mark and identifying a position relation between the base mark and the second alignment mark.
Semiconductor device mounting method
A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.
Semiconductor device mounting method
A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.
Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip (106), which is mounted with a first main surface (108) directly or indirectly on partial region of the first dielectric layer (104), a second substrate (110) over a second main surface (114) of the at least one electronic chip (106), and an electrical contacting (116) for the electric contact of the at least one electronic chip (106) through the first dielectric layer (104), wherein the first adhesion layer (104) on the first substrate (102) extends over an area, which exceeds the first main surface (108).
MODELING OF NANOPARTICLE AGGLOMERATION AND POWDER BED FORMATION IN MICROSCALE SELECTIVE LASER SINTERING SYSTEMS
Exemplified microscale selective laser sintering (μ-SLS or micro-SLS) systems and methods facilitate modeling of the nanoparticle powder bed by simulating the interactions between particles during the powder spreading operation. In particular, the exemplified methods and system use multiscale modeling techniques to accurately predict the formation and mechanical/electrical properties of parts produced by selective laser sintering of powder beds. Discrete element modeling is used for nanoscale particle interactions by implementing the different forces dominant at nanoscale. A heat transfer analysis is used to predict the sintering of individual particles in the powder beds in order to build up a complete structural model of the parts that are being produced by the SLS process.
Component mounting method
While a substrate is placed on a substrate placement stage provided in a central substrate transfer unit, the substrate is transferred to a component loading operation unit, after operation for loading a component on the substrate has been performed by the component loading operation unit, the central substrate transfer unit is moved to the side of a first component crimping operation unit to thereby transfer the substrate that remains placed on the substrate placement stage to the first component crimping operation unit, and the component is crimped to the substrate by the first component crimping operation unit.
Die Bonding Apparatus and Manufacturing Method for Semiconductor Device
A die bonding apparatus includes: a driven body; and a table for driving the driven body. The table includes: a base; a linear motor having a first mover that moves the driven body, and a stator; a first linear motion guide that is provided between the base and the stator and capable of freely moving the stator; a second linear motion guide that is provided between the base and the first mover and capable of freely moving the first mover; a second mover provided in the form of being fixed to the base; and a control device for controlling the first mover and the second mover. The control device is configured to move the stator along the first linear motion guide using the second mover.
Strain-induced shift mitigation in semiconductor packages
A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
SEMICONDUCTOR PACKAGES INCLUDING AT LEAST ONE DIE POSITION CHECKER
A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.